Imagen de Portada

FlowPlace: Flow Matching for Chip Placement

Fuente: arXiv

Guardado en:

Detalles Bibliográficos
Autores principales:	Xie, Peng, Xue, Ke, Shi, Yunqi, Chen, Ruo-Tong, Gao, Chengrui, Xu, Siyuan, Ding, Chenjian, Yuan, Mingxuan, Qian, Chao
Formato:	Preprint
Publicado:	2026
Materias:	Hardware Architecture Artificial Intelligence Machine Learning
Acceso en línea:	Acceder al recurso
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

Ejemplares similares

BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement
por: Xue, Ke, et al.
Publicado: (2025)

Timing-Driven Global Placement by Efficient Critical Path Extraction
por: Shi, Yunqi, et al.
Publicado: (2025)

Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation
por: Shi, Yunqi, et al.
Publicado: (2025)

Re$^{\text{2}}$MaP: Macro Placement by Recursively Prototyping and Packing Tree-based Relocating
por: Shi, Yunqi, et al.
Publicado: (2025)

Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms
por: Wang, Zhihai, et al.
Publicado: (2024)

Non-Overlapping Placement of Macro Cells based on Reinforcement Learning in Chip Design
por: Yu, Tao, et al.
Publicado: (2024)

PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies
por: Iff, Patrick, et al.
Publicado: (2025)

Escaping Flatland: A Placement Flow for Enabling 3D FPGAs
por: Hao, Cong, et al.
Publicado: (2026)

DiffPlace: A Conditional Diffusion Framework for Simultaneous VLSI Placement Beyond Sequential Paradigms
por: Trung, Kien Le, et al.
Publicado: (2025)

SuperFlow: A Fully-Customized RTL-to-GDS Design Automation Flow for Adiabatic Quantum-Flux-Parametron Superconducting Circuits
por: Xie, Yanyue, et al.
Publicado: (2024)

TransPlace: Transferable Circuit Global Placement via Graph Neural Network
por: Hou, Yunbo, et al.
Publicado: (2025)

Search-in-Memory (SiM): Reliable, Versatile, and Efficient Data Matching in SSD's NAND Flash Memory Chip for Data Indexing Acceleration
por: Chen, Yun-Chih, et al.
Publicado: (2024)

Chip Placement with Diffusion Models
por: Lee, Vint, et al.
Publicado: (2024)

AutoFlows++: Hierarchical Message Flow Mining for System on Chip Designs
por: Nadimi, Bardia, et al.
Publicado: (2026)

Aging Aware Adaptive Voltage Scaling for Reliable and Efficient AI Accelerators
por: Xie, Tong, et al.
Publicado: (2026)

Large Processor Chip Model
por: Chang, Kaiyan, et al.
Publicado: (2025)

Memory-efficient Sketch Acceleration for Handling Large Network Flows on FPGAs
por: Han, Zhaoyang, et al.
Publicado: (2025)

FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
por: Tong, Jianming, et al.
Publicado: (2024)

CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
por: Fang, Wenji, et al.
Publicado: (2025)

ChipLight: Cross-Layer Optimization of Chiplet Design with Optical Interconnects for LLM Training
por: Bai, Kangbo, et al.
Publicado: (2026)

Leveraging Application-Specific Knowledge for Energy-Efficient Deep Learning Accelerators on Resource-Constrained FPGAs
por: Qian, Chao
Publicado: (2025)

Control Flow Management in Modern GPUs
por: Shoushtary, Mojtaba Abaie, et al.
Publicado: (2024)

A Time- and Energy-Efficient CNN with Dense Connections on Memristor-Based Chips
por: Zhou, Wenyong, et al.
Publicado: (2025)

FastFlow in FPGA Stacks of Data Centers
por: Paul, Rourab, et al.
Publicado: (2024)

Breaking On-Chip Communication Anonymity using Flow Correlation Attacks
por: Weerasena, Hansika, et al.
Publicado: (2023)

Optimized Spatial Architecture Mapping Flow for Transformer Accelerators
por: Xu, Haocheng, et al.
Publicado: (2024)

Efficient Sparse Processing-in-Memory Architecture (ESPIM) for Machine Learning Inference
por: He, Mingxuan, et al.
Publicado: (2024)

Theseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models
por: Zhu, Jingchen, et al.
Publicado: (2024)

Decoupled Control Flow and Data Access in RISC-V GPGPUs
por: Sarda, Giuseppe M., et al.
Publicado: (2025)

WIP: Turning Fake Chips into Learning Opportunities
por: Mehraban, Haniye, et al.
Publicado: (2025)

TEMP: A Memory Efficient Physical-aware Tensor Partition-Mapping Framework on Wafer-scale Chips
por: Wang, Huizheng, et al.
Publicado: (2025)

LinkBo: An Adaptive Single-Wire, Low-Latency, and Fault-Tolerant Communications Interface for Variable-Distance Chip-to-Chip Systems
por: Ye, Bochen, et al.
Publicado: (2025)

ONNX-to-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs
por: Manca, Federico, et al.
Publicado: (2024)

Multi-Objective Optimization for Common-Centroid Placement of Analog Transistors
por: Maji, Supriyo, et al.
Publicado: (2024)

Analytical Heterogeneous Die-to-Die 3D Placement with Macros
por: Zhao, Yuxuan, et al.
Publicado: (2024)

Accelerating Electrostatics-based Global Placement with Enhanced FFT Computation
por: Zhang, Hangyu, et al.
Publicado: (2025)

Resilient and Secure Programmable System-on-Chip Accelerator Offload
por: Gouveia, Inês Pinto, et al.
Publicado: (2024)

DSLUT: An Asymmetric LUT and its Automatic Design Flow Based on Practical Functions
por: Yang, Moucheng, et al.
Publicado: (2025)

LLMulator: Generalizable Cost Modeling for Dataflow Accelerators with Input-Adaptive Control Flow
por: Chang, Kaiyan, et al.
Publicado: (2025)

Systolic Array Data Flows for Efficient Matrix Multiplication in Deep Neural Networks
por: Raja, Tejas
Publicado: (2024)