A PVT-Resilient Subthreshold SRAM-Based In-Memory Computing Accelerator with In-Situ Regulation for Energy-Efficient Spiking Neural Networks
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arXiv
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| Main Authors: | Kao, Shih-Hang, Hung, Yang-Chan, Wang, I-Wen, Liu, Bing-Han, Chen, Yu-Chia, Chang, Tian-Sheuan, Jou, Shyh-Jye, Liu, Chien-Nan, Chen, Hung-Ming, Chen, Wei-Zen |
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| Format: | Preprint |
| Published: |
2026
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