AMSnet-q: Unsupervised Circuit Identification and Performance Labeling for AMS Circuits
Fuente:
arXiv
Saved in:
| Main Authors: | , , , , , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2026
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866914526269538304 |
|---|---|
| author | Zhang, Ze Zhou, Junzhuo Shi, Yichen Tao, Zhuofu Ji, Rui Yu, Zhiping Chen, Quan Lin, Ting-Jung He, Lei |
| author_facet | Zhang, Ze Zhou, Junzhuo Shi, Yichen Tao, Zhuofu Ji, Rui Yu, Zhiping Chen, Quan Lin, Ting-Jung He, Lei |
| contents | Analog and mixed-signal (AMS) circuit design remains heavily reliant on expert knowledge. While recent AI-driven automation tools can generate candidate topologies, they critically depend on manually curated datasets with functional and performance annotations -- a requirement that current large language models (LLMs) and vision models cannot automate. Existing approaches still require domain experts to manually interpret circuit functionality.
We present AMSnet-q, a fully automated, unsupervised pipeline that eliminates human-in-the-loop annotation by converting schematic images directly into a labeled AMS circuit database. Unlike prior work that stops at netlist extraction, our framework automates the complete verification loop: it performs schematic-to-netlist conversion, topology-aware testbench generation, and simulation-based sizing validation to objectively determine circuit functionality. Validated in 28 nm technology, AMSnet-q processed 739 schematics from the AMSnet 1.0 dataset, automatically constructing a repository of 4 circuit classes, 105 distinct topologies, and 89,789 labeled device configurations. By decoupling human effort from dataset volume and reducing the workload to a one-time testbench template per circuit class, AMSnet-q enables scalable, objective, and fully automated AMS database construction. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_01404 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | AMSnet-q: Unsupervised Circuit Identification and Performance Labeling for AMS Circuits Zhang, Ze Zhou, Junzhuo Shi, Yichen Tao, Zhuofu Ji, Rui Yu, Zhiping Chen, Quan Lin, Ting-Jung He, Lei Hardware Architecture Artificial Intelligence Analog and mixed-signal (AMS) circuit design remains heavily reliant on expert knowledge. While recent AI-driven automation tools can generate candidate topologies, they critically depend on manually curated datasets with functional and performance annotations -- a requirement that current large language models (LLMs) and vision models cannot automate. Existing approaches still require domain experts to manually interpret circuit functionality. We present AMSnet-q, a fully automated, unsupervised pipeline that eliminates human-in-the-loop annotation by converting schematic images directly into a labeled AMS circuit database. Unlike prior work that stops at netlist extraction, our framework automates the complete verification loop: it performs schematic-to-netlist conversion, topology-aware testbench generation, and simulation-based sizing validation to objectively determine circuit functionality. Validated in 28 nm technology, AMSnet-q processed 739 schematics from the AMSnet 1.0 dataset, automatically constructing a repository of 4 circuit classes, 105 distinct topologies, and 89,789 labeled device configurations. By decoupling human effort from dataset volume and reducing the workload to a one-time testbench template per circuit class, AMSnet-q enables scalable, objective, and fully automated AMS database construction. |
| title | AMSnet-q: Unsupervised Circuit Identification and Performance Labeling for AMS Circuits |
| topic | Hardware Architecture Artificial Intelligence |
| url | https://arxiv.org/abs/2605.01404 |