Imagen de Portada

Understanding Simulated Architecture via gem5 Call-Stack Profiling

Fuente: arXiv

Guardado en:

Detalles Bibliográficos
Autores principales:	Söderström, Johan, Aligholipour, Rashid, Yao, Yuan
Formato:	Preprint
Publicado:	2026
Materias:	Hardware Architecture
Acceso en línea:	Acceder al recurso
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

Ejemplares similares

Anatomy of the gem5 Simulator: AtomicSimpleCPU, TimingSimpleCPU, O3CPU, and Their Interaction with the Ruby Memory System
por: Söderström, Johan, et al.
Publicado: (2025)

Toward Reproducible and Standardized Computer Architecture Simulation with gem5
por: Pai, Kunal, et al.
Publicado: (2025)

gem5 Co-Pilot: AI Assistant Agent for Architectural Design Space Exploration
por: Fu, Zuoming, et al.
Publicado: (2025)

Adding MFMA Support to gem5
por: Kurzynski, Marco, et al.
Publicado: (2025)

Architecture, Simulation and Software Stack to Support Post-CMOS Accelerators: The ARCHYTAS Project
por: Agosta, Giovanni, et al.
Publicado: (2025)

parti-gem5: gem5's Timing Mode Parallelised
por: Cubero-Cascante, José, et al.
Publicado: (2023)

CHAOS: Controlled Hardware fAult injectOr System for gem5
por: Vinciguerra, Elio, et al.
Publicado: (2026)

Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension
por: Fragkoulis, George-Marios, et al.
Publicado: (2024)

Survey on Characterizing and Understanding GNNs from a Computer Architecture Perspective
por: Wu, Meng, et al.
Publicado: (2024)

Tasa: Thermal-aware 3D-Stacked Architecture Design with Bandwidth Sharing for LLM Inference
por: He, Siyuan, et al.
Publicado: (2025)

A Mess of Memory System Benchmarking, Simulation and Application Profiling
por: Esmaili-Dokht, Pouya, et al.
Publicado: (2024)

Energy-Oriented Computing Architecture Simulator for SNN Training
por: Ma, Yunhao, et al.
Publicado: (2025)

Profile-Guided Temporal Prefetching
por: Li, Mengming, et al.
Publicado: (2025)

FastFlow in FPGA Stacks of Data Centers
por: Paul, Rourab, et al.
Publicado: (2024)

A Full-Stack Performance Evaluation Infrastructure for 3D-DRAM-based LLM Accelerators
por: Li, Cong, et al.
Publicado: (2026)

WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes
por: Giorgi, Roberto, et al.
Publicado: (2025)

FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling
por: Zhang, Qijun, et al.
Publicado: (2024)

Beehive: A Flexible Network Stack for Direct-Attached Accelerators
por: Lim, Katie, et al.
Publicado: (2024)

Energy-Efficient p-Bit-Based Fully-Connected Quantum-Inspired Simulated Annealer with Dual BRAM Architecture
por: Onizawa, Naoya, et al.
Publicado: (2026)

AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
por: Zhang, Qijun, et al.
Publicado: (2025)

XtraMAC: An Efficient MAC Architecture for Mixed-Precision LLM Inference on FPGA
por: Yu, Feng, et al.
Publicado: (2026)

UpANNS: Enhancing Billion-Scale ANNS Efficiency with Real-World PIM Architecture
por: Chen, Sitian, et al.
Publicado: (2024)

ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework
por: Zhang, Qijun, et al.
Publicado: (2025)

SimulatorCoder: DNN Accelerator Simulator Code Generation and Optimization via Large Language Models
por: Xia, Yuhuan, et al.
Publicado: (2026)

Simulation-Driven Evaluation of Chiplet-Based Architectures Using VisualSim
por: Ali, Wajid, et al.
Publicado: (2025)

CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST
por: Goswami, Kaustav, et al.
Publicado: (2026)

OffRAC: Offloading Through Remote Accelerator Calls
por: Yang, Ziyi, et al.
Publicado: (2025)

Microbenchmarking NVIDIA's Blackwell Architecture: An in-depth Architectural Analysis
por: Jarmusch, Aaron, et al.
Publicado: (2025)

Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication
por: Nojehdeh, Mohammadreza Esmali, et al.
Publicado: (2025)

Splatonic: Architecture Support for 3D Gaussian Splatting SLAM via Sparse Processing
por: Huang, Xiaotong, et al.
Publicado: (2025)

A Switch-Centric In-Network Architecture for Accelerating LLM Inference in Shared-Memory Network
por: Jiang, Aojie, et al.
Publicado: (2026)

Mozart: Modularized and Efficient MoE Training on 3.5D Wafer-Scale Chiplet Architectures
por: Luo, Shuqing, et al.
Publicado: (2026)

MFIT: Multi-Fidelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures
por: Pfromm, Lukas, et al.
Publicado: (2024)

Workload-Aware Early-Stage Power Delivery Network Optimization via Architectural Power Traces
por: Hayes, Oran, et al.
Publicado: (2026)

Understanding Accelerator Compilers via Performance Profiling
por: Yorihiro, Ayaka, et al.
Publicado: (2025)

NDPage: Efficient Address Translation for Near-Data Processing Architectures via Tailored Page Table
por: Jiang, Qingcai, et al.
Publicado: (2025)

Modeling and Simulation Frameworks for Processing-in-Memory Architectures
por: Aghaei, Mahdi, et al.
Publicado: (2025)

Rethinking Compute Substrates for 3D-Stacked Near-Memory LLM Decoding: Microarchitecture-Scheduling Co-Design
por: Ai, Chenyang, et al.
Publicado: (2026)

Privacy-Preserving Performance Profiling of In-The-Wild GPUs
por: McDougall, Ian, et al.
Publicado: (2025)

Reconfigurable Stream Network Architecture
por: Wang, Chengyue, et al.
Publicado: (2024)