_version_ 1866909010492391424
author Madhav, Mahesh
Lee, Allen
Mejia, Andres
Moore, Branden
Soppadandi, Charan
Cambly, Chris
Müllner, Christoph
Bowers, Daniel
Reiner, David
Bakhvalov, Denis
Zhao, Di
Voth, Duane
Xue, Feng
Silber-Chaussumier, Frédérique
Bucek, James
Southern, James
Liu, Jiangning
Himer, Jim
Henning, John
Smith, Kevin
Yang, Kristen
Kashyap, Kunal
Guy, Mason
Colgrove, Mat
Berg, Michael
Battini, Prasad
Joshi, Prasad
Prasad, Rohit
Bhattacharya, Shayantika
Caculo, Sriyash
Reimbold, Stefan
Iyengar, Sundar
Smith, Van
Todorovski, Zarko
author_facet Madhav, Mahesh
Lee, Allen
Mejia, Andres
Moore, Branden
Soppadandi, Charan
Cambly, Chris
Müllner, Christoph
Bowers, Daniel
Reiner, David
Bakhvalov, Denis
Zhao, Di
Voth, Duane
Xue, Feng
Silber-Chaussumier, Frédérique
Bucek, James
Southern, James
Liu, Jiangning
Himer, Jim
Henning, John
Smith, Kevin
Yang, Kristen
Kashyap, Kunal
Guy, Mason
Colgrove, Mat
Berg, Michael
Battini, Prasad
Joshi, Prasad
Prasad, Rohit
Bhattacharya, Shayantika
Caculo, Sriyash
Reimbold, Stefan
Iyengar, Sundar
Smith, Van
Todorovski, Zarko
contents The march toward developing relevant and robust CPU benchmarks continues with the introduction of SPEC CPU 2026, the next generation suite for measuring processor performance. This paper details the methodology behind its creation, showcasing a process centered on community collaboration and principled development. The suite is built upon a foundation of modern, open-source applications, selected and hardened through a process that emphasizes workload diversity, portability, and software longevity. A key contribution is Rolling-Round-Robin Rate, a novel and standardized approach to running heterogeneous, multiprogrammed workloads that addresses a long-standing gap in benchmarking practice. Additionally, the suite features an expanded set of multithreaded benchmarks and introduces workloads with distinct microarchitectural profiles, reflecting the demands of contemporary software. By detailing our principled approach to benchmark selection, adaptation, and validation, we demonstrate how the SPEC CPU 2026 suite sets the standard for performance evaluation in the next era of computer architecture research and development.
format Preprint
id arxiv_https___arxiv_org_abs_2605_01575
institution arXiv
publishDate 2026
record_format arxiv
spellingShingle SPEC CPU: The Next Generation
Madhav, Mahesh
Lee, Allen
Mejia, Andres
Moore, Branden
Soppadandi, Charan
Cambly, Chris
Müllner, Christoph
Bowers, Daniel
Reiner, David
Bakhvalov, Denis
Zhao, Di
Voth, Duane
Xue, Feng
Silber-Chaussumier, Frédérique
Bucek, James
Southern, James
Liu, Jiangning
Himer, Jim
Henning, John
Smith, Kevin
Yang, Kristen
Kashyap, Kunal
Guy, Mason
Colgrove, Mat
Berg, Michael
Battini, Prasad
Joshi, Prasad
Prasad, Rohit
Bhattacharya, Shayantika
Caculo, Sriyash
Reimbold, Stefan
Iyengar, Sundar
Smith, Van
Todorovski, Zarko
Performance
Hardware Architecture
68U01
B.8.2; C.4
The march toward developing relevant and robust CPU benchmarks continues with the introduction of SPEC CPU 2026, the next generation suite for measuring processor performance. This paper details the methodology behind its creation, showcasing a process centered on community collaboration and principled development. The suite is built upon a foundation of modern, open-source applications, selected and hardened through a process that emphasizes workload diversity, portability, and software longevity. A key contribution is Rolling-Round-Robin Rate, a novel and standardized approach to running heterogeneous, multiprogrammed workloads that addresses a long-standing gap in benchmarking practice. Additionally, the suite features an expanded set of multithreaded benchmarks and introduces workloads with distinct microarchitectural profiles, reflecting the demands of contemporary software. By detailing our principled approach to benchmark selection, adaptation, and validation, we demonstrate how the SPEC CPU 2026 suite sets the standard for performance evaluation in the next era of computer architecture research and development.
title SPEC CPU: The Next Generation
topic Performance
Hardware Architecture
68U01
B.8.2; C.4
url https://arxiv.org/abs/2605.01575