PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation

Fuente: arXiv

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Bibliographic Details
Main Authors:	Yin, Shuo, Liu, Fangzhou, Zou, Lancheng, Fu, Rongliang, Zhao, Wenqian, Bai, Chen, Ho, Tsung-Yi, Xie, Yuan, Yu, Bei
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2605.01836