Copertina

Monolithic 3D Integration for Null Convention Logic (NCL)-Based Asynchronous Circuits

Fuente: arXiv

Salvato in:

Dettagli Bibliografici
Autori principali:	Zhang, Xiameng, Ponugoti, Kushal, Sakib, Ashiq, Vemuri, Madhava
Natura:	Preprint
Pubblicazione:	2026
Soggetti:	Hardware Architecture Emerging Technologies
Accesso online:	Acceder al recurso
Tags:	Aggiungi Tag Nessun Tag, puoi essere il primo ad aggiungerne!!

Documenti analoghi

ARMAN: A Reconfigurable Monolithic 3D Accelerator Architecture for Convolutional Neural Networks
di: Sedaghatgoo, Ali, et al.
Pubblicazione: (2024)

Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits
di: Chen, Yibo, et al.
Pubblicazione: (2025)

ANCoEF: Asynchronous Neuromorphic Algorithm/Hardware Co-Exploration Framework with a Fully Asynchronous Simulator
di: Zhang, Jian, et al.
Pubblicazione: (2024)

Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock
di: Choi, Suhyeong, et al.
Pubblicazione: (2024)

Fine Grain 3D Integration for Microarchitecture Design Through Cube Packing Exploration
di: Liu, Yongxiang, et al.
Pubblicazione: (2025)

Hardware Accelerators for Artificial Intelligence
di: Ahsan, S M Mojahidul, et al.
Pubblicazione: (2024)

A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical Functions
di: M, Amogh K, et al.
Pubblicazione: (2025)

The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models
di: Chen, Lei, et al.
Pubblicazione: (2024)

Scaling up Reversible Logic with HKI Superconducting Inductors
di: DeBenedictis, Erik P.
Pubblicazione: (2025)

STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration
di: Parekh, Varun Darshana, et al.
Pubblicazione: (2025)

Length-Matching Routing for Programmable Photonic Circuits Using Best-First Strategy
di: Wang, Xiaoke, et al.
Pubblicazione: (2025)

SuperFlow: A Fully-Customized RTL-to-GDS Design Automation Flow for Adiabatic Quantum-Flux-Parametron Superconducting Circuits
di: Xie, Yanyue, et al.
Pubblicazione: (2024)

Stratum: System-Hardware Co-Design with Tiered Monolithic 3D-Stackable DRAM for Efficient MoE Serving
di: Pan, Yue, et al.
Pubblicazione: (2025)

AnalogToBi: Device-Level Analog Circuit Topology Generation via Bipartite Graph and Grammar Guided Decoding
di: Kim, Seungmin, et al.
Pubblicazione: (2026)

Device-Circuit Co-Design of Variation-Resilient Read and Write Drivers for Antiferromagnetic Tunnel Junction (AFMTJ) Memories
di: Choudhary, Yousuf, et al.
Pubblicazione: (2026)

Opportunities and Challenges for 3D Systems and Their Design
di: Emma, Philip, et al.
Pubblicazione: (2025)

Design of a 64-bit SQRT-CSLA with Reduced Area and High-Speed Applications in Low Power VLSI Circuits
di: Pallavi, CH., et al.
Pubblicazione: (2024)

Single-Cell Universal Logic-in-Memory Using 2T-nC FeRAM: An Area and Energy-Efficient Approach for Bulk Bitwise Computation
di: Biswas, Rudra, et al.
Pubblicazione: (2025)

SKYLIGHT: A Scalable Hundred-Channel 3D Photonic In-Memory Tensor Core Architecture for Real-time AI Inference
di: Zhang, Meng, et al.
Pubblicazione: (2026)

High-Performance Data Mapping for BNNs on PCM-based Integrated Photonics
di: Shahroodi, Taha, et al.
Pubblicazione: (2024)

Toward Digital Twins in 3D IC Packaging: A Critical Review of Physics, Data, and Hybrid Architectures
di: Datta, Gourab, et al.
Pubblicazione: (2026)

A Low-Cost Reliable Racetrack Cache Based on Data Compression
di: Cheshmikhani, Elham, et al.
Pubblicazione: (2025)

NeRTCAM: CAM-Based CMOS Implementation of Reference Frames for Neuromorphic Processors
di: Nair, Harideep, et al.
Pubblicazione: (2024)

H3PIMAP: A Heterogeneity-Aware Multi-Objective DNN Mapping Framework on Electronic-Photonic Processing-in-Memory Architectures
di: Yin, Ziang, et al.
Pubblicazione: (2025)

A Novel Low-Power Cache Architecture Based on 6-Transistor SRAM Cells
di: Dizabadi, Naser Khatti, et al.
Pubblicazione: (2026)

CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval
di: Li, Xinzhao, et al.
Pubblicazione: (2026)

Stoch-IMC: A Bit-Parallel Stochastic In-Memory Computing Architecture Based on STT-MRAM
di: Hajisadeghi, Amir M., et al.
Pubblicazione: (2024)

Scattering-Matrix-Based Parametric Characterization of a Two-Port Bridged-T Network for Microstrip Filter Applications
di: Dizabadi, Naser Khatti, et al.
Pubblicazione: (2026)

ReCross: Efficient Embedding Reduction Scheme for In-Memory Computing using ReRAM-Based Crossbar
di: Lai, Yu-Hong, et al.
Pubblicazione: (2025)

A Reconfigurable Time-Domain In-Memory Computing Macro using FeFET-Based CAM with Multilevel Delay Calibration in 28 nm CMOS
di: Mattar, Jeries, et al.
Pubblicazione: (2025)

Fully Automated Verification Framework for Configurable IPs: From Requirements to Results
di: Zhang, Shuhang, et al.
Pubblicazione: (2025)

Running Conventional Automatic Speech Recognition on Memristor Hardware: A Simulated Approach
di: Rossenbach, Nick, et al.
Pubblicazione: (2025)

Scalable Digital Compute-in-Memory Ising Machines for Robustness Verification of Binary Neural Networks
di: Vadlamani, Madhav, et al.
Pubblicazione: (2026)

TLGLock: A New Approach in Logic Locking Using Key-Driven Charge Recycling in Threshold Logic Gates
di: Sahruri, Abdullah, et al.
Pubblicazione: (2025)

A Novel Thermal Network Model and Electro-Thermal Coupling Study for NSFETs and CFETs Considering Thermal Crosstalk
di: Miao, Tianci, et al.
Pubblicazione: (2025)

CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation
di: Wang, Yanjing, et al.
Pubblicazione: (2024)

SCATTER: Algorithm-Circuit Co-Sparse Photonic Accelerator with Thermal-Tolerant, Power-Efficient In-situ Light Redistribution
di: Yin, Ziang, et al.
Pubblicazione: (2024)

Maximizing Memory-Level Parallelism via Integrated Stochastic Logic-in-Memory Architectures
di: Razi, Farzad, et al.
Pubblicazione: (2026)

Pinball: A Cryogenic Predecoder for Surface Code Decoding Under Circuit-Level Noise
di: Knapen, Alexander, et al.
Pubblicazione: (2025)

ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
di: Tsaras, Dimitris, et al.
Pubblicazione: (2025)