Design and Implementation of BNN-Based Object Detection on FPGA
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arXiv
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| Main Authors: | , , , , , , , |
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| Format: | Preprint |
| Published: |
2026
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| _version_ | 1866915997226631168 |
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| author | Zhao, Xuyu Wu, Yunpeng Zhu, Mengyuan Huang, Haoyu Xu, Xiaoyu Li, Yanjing Zhang, Gaolong Zhang, Baochang |
| author_facet | Zhao, Xuyu Wu, Yunpeng Zhu, Mengyuan Huang, Haoyu Xu, Xiaoyu Li, Yanjing Zhang, Gaolong Zhang, Baochang |
| contents | This paper implements a Binary Neural Network (BNN) based YOLOv3-tiny-like object detector on a low-cost FPGA. The network takes 320*320*3 RGB images as input. Its main convolution layers use 1-bit weights and 8-bit activations, while Conv1 and the final detection head use fixed-point standard convolutions. From the trained ONNX model, weights, biases, and quantization parameters are extracted, converted to fixed point, packed into COE files, and stored in Vivado BRAM ROMs. The hardware is written fully in Verilog RTL and includes padding, line buffering, binary convolution, quantization post-processing, max pooling, and detection-head computation. For layers where Mul_prev is indexed by input channel and Div_current by output channel, Mul_prev is fused in-to the BNN PE so that channel-wise compensation is applied during accumulation. On VOC, the model obtains 39.6% mAP50 with 0.098 GFLOPs and 0.74 M parameters. RTL simulation shows that the final raw detection output reaches a correlation coefficient of 0.999964 and a mean absolute error of 0.020027 against the corresponding ONNX node. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_03396 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Design and Implementation of BNN-Based Object Detection on FPGA Zhao, Xuyu Wu, Yunpeng Zhu, Mengyuan Huang, Haoyu Xu, Xiaoyu Li, Yanjing Zhang, Gaolong Zhang, Baochang Hardware Architecture This paper implements a Binary Neural Network (BNN) based YOLOv3-tiny-like object detector on a low-cost FPGA. The network takes 320*320*3 RGB images as input. Its main convolution layers use 1-bit weights and 8-bit activations, while Conv1 and the final detection head use fixed-point standard convolutions. From the trained ONNX model, weights, biases, and quantization parameters are extracted, converted to fixed point, packed into COE files, and stored in Vivado BRAM ROMs. The hardware is written fully in Verilog RTL and includes padding, line buffering, binary convolution, quantization post-processing, max pooling, and detection-head computation. For layers where Mul_prev is indexed by input channel and Div_current by output channel, Mul_prev is fused in-to the BNN PE so that channel-wise compensation is applied during accumulation. On VOC, the model obtains 39.6% mAP50 with 0.098 GFLOPs and 0.74 M parameters. RTL simulation shows that the final raw detection output reaches a correlation coefficient of 0.999964 and a mean absolute error of 0.020027 against the corresponding ONNX node. |
| title | Design and Implementation of BNN-Based Object Detection on FPGA |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2605.03396 |