The Anatomy of Silent Data Corruption: GPU Error Pattern Study and Modeling Guidance
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| Main Authors: | , , , , , , , |
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| Format: | Preprint |
| Published: |
2026
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| _version_ | 1866909014882779136 |
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| author | Tung, Chung-Hsuan Huang, Yanxiang Saxena, Nirmal Shirvani, Philip Hukerikar, Saurabh Jain, Twinkle Tyagi, Abhishek Gongalore, Sanjay |
| author_facet | Tung, Chung-Hsuan Huang, Yanxiang Saxena, Nirmal Shirvani, Philip Hukerikar, Saurabh Jain, Twinkle Tyagi, Abhishek Gongalore, Sanjay |
| contents | Silent data corruption (SDC) threatens the reliability of large-scale GPU clusters used for training large language models, yet its rarity and lack of explicit error signals make accurate high-level modeling challenging. To address this gap, we conducted a large-scale gate-level stuck-at fault injection on a production-class data-center GPU, consuming over three million simulator hours across 63 CUDA micro-benchmarks. We extracted GPU SDC characteristics in terms of corruption types, bit-flip behavior, and warp-aligned spatial correlation. Our results show that NaN/+INF/-INF account for only 1.01% of SDC outcomes, that single-bit flips constitute less than 40% of bit-flip events, and that corruption addresses exhibit periodicity. These statistics motivate distribution-aware high-level fault modeling and realistic software-based fault injection for resilience evaluation of production-class GPU architectures. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_04213 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | The Anatomy of Silent Data Corruption: GPU Error Pattern Study and Modeling Guidance Tung, Chung-Hsuan Huang, Yanxiang Saxena, Nirmal Shirvani, Philip Hukerikar, Saurabh Jain, Twinkle Tyagi, Abhishek Gongalore, Sanjay Hardware Architecture Silent data corruption (SDC) threatens the reliability of large-scale GPU clusters used for training large language models, yet its rarity and lack of explicit error signals make accurate high-level modeling challenging. To address this gap, we conducted a large-scale gate-level stuck-at fault injection on a production-class data-center GPU, consuming over three million simulator hours across 63 CUDA micro-benchmarks. We extracted GPU SDC characteristics in terms of corruption types, bit-flip behavior, and warp-aligned spatial correlation. Our results show that NaN/+INF/-INF account for only 1.01% of SDC outcomes, that single-bit flips constitute less than 40% of bit-flip events, and that corruption addresses exhibit periodicity. These statistics motivate distribution-aware high-level fault modeling and realistic software-based fault injection for resilience evaluation of production-class GPU architectures. |
| title | The Anatomy of Silent Data Corruption: GPU Error Pattern Study and Modeling Guidance |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2605.04213 |