UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
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arXiv
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| Autori principali: | , , , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2026
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| _version_ | 1866910195134758912 |
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| author | Ye, Junhao Pan, Dingrong Liu, Hanyuan Hu, Yuchen Zhou, Jie Xu, Ke Fang, Xinwei Wang, Xi Guan, Nan Jiang, Zhe |
| author_facet | Ye, Junhao Pan, Dingrong Liu, Hanyuan Hu, Yuchen Zhou, Jie Xu, Ke Fang, Xinwei Wang, Xi Guan, Nan Jiang, Zhe |
| contents | Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of total effort. While the Universal Verification Methodology (UVM) improves reuse through structured verification environments, constructing subsystem-level UVM testbenches and generating high-quality stimuli still require extensive manual coding, repeated EDA tool runs, and deep protocol and micro-architectural expertise. We present UVMarvel, an automated verification framework that leverages Large Language Models (LLMs) to build UVM testbenches for subsystem-level RTL. UVMarvel introduces an Intermediate Representation (IR) and a Bus Protocol Library to translate heterogeneous specifications into protocol-correct subsystem-level UVM testbenches, and employs a Signal Tracker and a Verilog Patching Library to guide LLM-based stimuli refinement. UVMarvel is the first framework capable of automatically constructing subsystem-level UVM testbenches across mainstream bus protocols, and it achieves an average code coverage of 95.65%, while reducing verification time from several human working days to a 4.5-hour automated execution. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_04704 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification Ye, Junhao Pan, Dingrong Liu, Hanyuan Hu, Yuchen Zhou, Jie Xu, Ke Fang, Xinwei Wang, Xi Guan, Nan Jiang, Zhe Hardware Architecture Software Engineering Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of total effort. While the Universal Verification Methodology (UVM) improves reuse through structured verification environments, constructing subsystem-level UVM testbenches and generating high-quality stimuli still require extensive manual coding, repeated EDA tool runs, and deep protocol and micro-architectural expertise. We present UVMarvel, an automated verification framework that leverages Large Language Models (LLMs) to build UVM testbenches for subsystem-level RTL. UVMarvel introduces an Intermediate Representation (IR) and a Bus Protocol Library to translate heterogeneous specifications into protocol-correct subsystem-level UVM testbenches, and employs a Signal Tracker and a Verilog Patching Library to guide LLM-based stimuli refinement. UVMarvel is the first framework capable of automatically constructing subsystem-level UVM testbenches across mainstream bus protocols, and it achieves an average code coverage of 95.65%, while reducing verification time from several human working days to a 4.5-hour automated execution. |
| title | UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification |
| topic | Hardware Architecture Software Engineering |
| url | https://arxiv.org/abs/2605.04704 |