XtraMAC: An Efficient MAC Architecture for Mixed-Precision LLM Inference on FPGA
Fuente:
arXiv
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| Main Authors: | Yu, Feng, Tan, Hongshi, Chen, Yao, Wong, Weng-Fai, He, Bingsheng |
|---|---|
| Format: | Preprint |
| Published: |
2026
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| Subjects: | |
| Online Access: | |
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