Development of embedded target detection system based on FPGA and YOLOv3-Tiny
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arXiv
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| Format: | Preprint |
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2026
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| _version_ | 1866915989931687936 |
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| author | Jiang, Zihan Liu, Fanghao Wang, Huawei Mattohti, Mamataziz Chen, Xiangquan Guo, Jingfu Wu, Xiaotian Dong, Yongjun |
| author_facet | Jiang, Zihan Liu, Fanghao Wang, Huawei Mattohti, Mamataziz Chen, Xiangquan Guo, Jingfu Wu, Xiaotian Dong, Yongjun |
| contents | Computational complexity and storage requirements are crucial factors influencing the performance and efficiency of convolutional neural networks (CNNs) in resource-constrained environments. This paper presents a high-performance embedded target detection system based on FPGA and YOLOv3-Tiny, specifically designed for embedded artificial intelligence applications. By integrating lightweight CNN optimization techniques with hardware accelerator design, significant improvements are made in both computational efficiency and resource utilization. Key optimizations, including low-bit quantization, batch normalization fusion, and table lookup mapping, reduce model parameters and computational complexity. Additionally, an FPGA hardware accelerator with a pipelined architecture is developed to enhance the efficiency of convolution operations while minimizing off-chip data transmission through modular design and on-chip cache optimization. On the ZYNQ-XC7Z035 platform, the system achieves an inference latency of 0.211 seconds, outperforming comparable designs by 75.58% in speed. The system achieves an power efficiency of 10.11 GOPS/W, surpassing comparable designs by at least 29.45%. Furthermore, hardware resource utilization is reduced by up to 51.94% compared to similar systems. This study offers innovative design methodologies and practical application examples for the efficient deployment of deep learning models on embedded platforms. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_06745 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Development of embedded target detection system based on FPGA and YOLOv3-Tiny Jiang, Zihan Liu, Fanghao Wang, Huawei Mattohti, Mamataziz Chen, Xiangquan Guo, Jingfu Wu, Xiaotian Dong, Yongjun Chemical Physics Hardware Architecture Computational complexity and storage requirements are crucial factors influencing the performance and efficiency of convolutional neural networks (CNNs) in resource-constrained environments. This paper presents a high-performance embedded target detection system based on FPGA and YOLOv3-Tiny, specifically designed for embedded artificial intelligence applications. By integrating lightweight CNN optimization techniques with hardware accelerator design, significant improvements are made in both computational efficiency and resource utilization. Key optimizations, including low-bit quantization, batch normalization fusion, and table lookup mapping, reduce model parameters and computational complexity. Additionally, an FPGA hardware accelerator with a pipelined architecture is developed to enhance the efficiency of convolution operations while minimizing off-chip data transmission through modular design and on-chip cache optimization. On the ZYNQ-XC7Z035 platform, the system achieves an inference latency of 0.211 seconds, outperforming comparable designs by 75.58% in speed. The system achieves an power efficiency of 10.11 GOPS/W, surpassing comparable designs by at least 29.45%. Furthermore, hardware resource utilization is reduced by up to 51.94% compared to similar systems. This study offers innovative design methodologies and practical application examples for the efficient deployment of deep learning models on embedded platforms. |
| title | Development of embedded target detection system based on FPGA and YOLOv3-Tiny |
| topic | Chemical Physics Hardware Architecture |
| url | https://arxiv.org/abs/2605.06745 |