A Fully Tunable Ultra-Low Power Current-Mode Memory Cell in Standard CMOS Technology
Fuente:
arXiv
Enregistré dans:
| Auteurs principaux: | , , , , |
|---|---|
| Format: | Preprint |
| Publié: |
2026
|
| Sujets: | |
| Accès en ligne: | |
| Tags: |
Ajouter un tag
Pas de tags, Soyez le premier à ajouter un tag!
|
| _version_ | 1866910231420731392 |
|---|---|
| author | Fyon, Arthur Mendolia, Loris Redouté, Jean-Michel Franci, Alessio Drion, Guillaume |
| author_facet | Fyon, Arthur Mendolia, Loris Redouté, Jean-Michel Franci, Alessio Drion, Guillaume |
| contents | This work introduces a fully tunable, ultra-low power unipolar memory cell inspired by the Schmitt-trigger comparator and designed in CMOS using only nine transistors. The proposed circuit operates entirely in the current domain and exploits a novel feedback configuration between two interdependent Heaviside-like thresholding elements to produce tunable bistable switching behavior. Its three key parameters-threshold current, hysteresis width, and output gain-are independently tunable via programmable bias currents, enabling flexibility across diverse analog computing applications. Unlike prior Schmitt-trigger designs, it simultaneously achieves current-mode operation, nanowatt-range power consumption, temperature stability, and full tunability, solely using standard MOSFET elements. Schematic-level simulations in a 180 nm CMOS process confirm robust hysteresis and resilience to device mismatch. Building on this circuit, we develop a complete family of spike-based logic gates using three-level current encoding, where the bistable memory retains the polarity of the last spike on each input indefinitely, enabling asynchronous logic operations without temporal windowing or refresh mechanisms. The same circuit also serves as the primitive for Bistable Memory Recurrent Units in analog neural networks, where the quantized hidden states provide inherent noise immunity. Together, these capabilities position the design as a versatile building block for next-generation neuromorphic processors integrating memory, logic, and recurrent computation. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_07936 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | A Fully Tunable Ultra-Low Power Current-Mode Memory Cell in Standard CMOS Technology Fyon, Arthur Mendolia, Loris Redouté, Jean-Michel Franci, Alessio Drion, Guillaume Signal Processing This work introduces a fully tunable, ultra-low power unipolar memory cell inspired by the Schmitt-trigger comparator and designed in CMOS using only nine transistors. The proposed circuit operates entirely in the current domain and exploits a novel feedback configuration between two interdependent Heaviside-like thresholding elements to produce tunable bistable switching behavior. Its three key parameters-threshold current, hysteresis width, and output gain-are independently tunable via programmable bias currents, enabling flexibility across diverse analog computing applications. Unlike prior Schmitt-trigger designs, it simultaneously achieves current-mode operation, nanowatt-range power consumption, temperature stability, and full tunability, solely using standard MOSFET elements. Schematic-level simulations in a 180 nm CMOS process confirm robust hysteresis and resilience to device mismatch. Building on this circuit, we develop a complete family of spike-based logic gates using three-level current encoding, where the bistable memory retains the polarity of the last spike on each input indefinitely, enabling asynchronous logic operations without temporal windowing or refresh mechanisms. The same circuit also serves as the primitive for Bistable Memory Recurrent Units in analog neural networks, where the quantized hidden states provide inherent noise immunity. Together, these capabilities position the design as a versatile building block for next-generation neuromorphic processors integrating memory, logic, and recurrent computation. |
| title | A Fully Tunable Ultra-Low Power Current-Mode Memory Cell in Standard CMOS Technology |
| topic | Signal Processing |
| url | https://arxiv.org/abs/2605.07936 |