Cover Image

TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Meng, Chang, Wang, Hanyu, Ye, Yuyang, Yu, Mingfei, Burleson, Wayne, De Micheli, Giovanni
Format:	Preprint
Published:	2026
Subjects:	Machine Learning Artificial Intelligence Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Low Power Approximate Multiplier Architecture for Deep Neural Networks
by: Jaswal, Pragun, et al.
Published: (2025)

Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators
by: Vellaisamy, Prabhu, et al.
Published: (2026)

AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators
by: Taheri, Mahdi, et al.
Published: (2024)

ApproXAI: Energy-Efficient Hardware Acceleration of Explainable AI using Approximate Computing
by: Siddique, Ayesha, et al.
Published: (2025)

Shavette: Low Power Neural Network Acceleration via Algorithm-level Error Detection and Undervolting
by: Rinkinen, Mikael, et al.
Published: (2024)

Accelerating MRI Uncertainty Estimation with Mask-based Bayesian Neural Network
by: Zhang, Zehuan, et al.
Published: (2024)

LLM-DSE: Searching Accelerator Parameters with LLM Agents
by: Wang, Hanyu, et al.
Published: (2025)

Building Reliable Arithmetic Multipliers Under NBTI Aging and Process Variations
by: Heidary, Masoud, et al.
Published: (2026)

YOCO: A Hybrid In-Memory Computing Architecture with 8-bit Sub-PetaOps/W In-Situ Multiply Arithmetic for Large-Scale AI
by: Xuan, Zihao, et al.
Published: (2023)

A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
by: Jaswal, Pragun, et al.
Published: (2026)

Neuromorphic Computing for Low-Power Artificial Intelligence
by: Katti, Keshava, et al.
Published: (2026)

Exploring the Potential of Wireless-enabled Multi-Chip AI Accelerators
by: Irabor, Emmanuel, et al.
Published: (2025)

A3D: Agentic AI flow for autonomous Accelerator Design
by: Nallathambi, Abinand, et al.
Published: (2026)

Chiplet-Based RISC-V SoC with Modular AI Acceleration
by: Bharadwaj, Suhas Suresh, et al.
Published: (2025)

AI-Powered Agile Analog Circuit Design and Optimization
by: Hu, Jinhai, et al.
Published: (2025)

A Low-Power Streaming Speech Enhancement Accelerator For Edge Devices
by: Wu, Ci-Hao, et al.
Published: (2025)

Dynamic Gradient Sparse Update for Edge Training
by: Li, I-Hsuan, et al.
Published: (2025)

Using the Abstract Computer Architecture Description Language to Model AI Hardware Accelerators
by: Müller, Mika Markus, et al.
Published: (2024)

Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE
by: Ahmad, Adeel, et al.
Published: (2025)

Expert Streaming: Accelerating Low-Batch MoE Inference via Multi-chiplet Architecture and Dynamic Expert Trajectory Scheduling
by: Ma, Songchen, et al.
Published: (2026)

MICSim: A Modular Simulator for Mixed-signal Compute-in-Memory based AI Accelerator
by: Wang, Cong, et al.
Published: (2024)

Learning in Log-Domain: Subthreshold Analog AI Accelerator Based on Stochastic Gradient Descent
by: Tageldeen, Momen K, et al.
Published: (2025)

Architectural Design and Performance Analysis of FPGA based AI Accelerators: A Comprehensive Review
by: Chatterjee, Soumita, et al.
Published: (2026)

Idle is the New Sleep: Configuration-Aware Alternative to Powering Off FPGA-Based DL Accelerators During Inactivity
by: Qian, Chao, et al.
Published: (2024)

HALO: Memory-Centric Heterogeneous Accelerator with 2.5D Integration for Low-Batch LLM Inference
by: Negi, Shubham, et al.
Published: (2025)

Hybrid Systolic Array Accelerator with Optimized Dataflow for Edge Large Language Model Inference
by: Chen, Chun-Ting, et al.
Published: (2025)

Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs
by: Vellaisamy, Prabhu, et al.
Published: (2024)

HH-PIM: Dynamic Optimization of Power and Performance with Heterogeneous-Hybrid PIM for Edge AI Devices
by: Jeon, Sangmin, et al.
Published: (2025)

J3DAI: A tiny DNN-Based Edge AI Accelerator for 3D-Stacked CMOS Image Sensor
by: Tain, Benoit, et al.
Published: (2025)

Achieving Trustworthy Real-Time Decision Support Systems with Low-Latency Interpretable AI Models
by: Deng, Zechun, et al.
Published: (2025)

DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference
by: Sonnino, Lorenzo, et al.
Published: (2023)

ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
by: Yu, Zhongkai, et al.
Published: (2026)

HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs
by: Meng, Chang-Chih, et al.
Published: (2026)

Enabling Unstructured Sparse Acceleration on Structured Sparse Accelerators
by: Jeong, Geonhwa, et al.
Published: (2024)

Power Stabilization for AI Training Datacenters
by: Choukse, Esha, et al.
Published: (2025)

LUT-DLA: Lookup Table as Efficient Extreme Low-Bit Deep Learning Accelerator
by: Li, Guoyu, et al.
Published: (2025)

Heterogeneous Acceleration Pipeline for Recommendation System Training
by: Adnan, Muhammad, et al.
Published: (2022)

MARCA: Mamba Accelerator with ReConfigurable Architecture
by: Li, Jinhao, et al.
Published: (2024)

ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
by: Zhang, Qijun, et al.
Published: (2025)

ChatEDA: A Large Language Model Powered Autonomous Agent for EDA
by: He, Zhuolun, et al.
Published: (2023)