DSPE: An Energy-Efficient Edge Processor for DeepSeek Inference with MerkleTree-based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing
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arXiv
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| Autori principali: | , , , , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2026
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| _version_ | 1866914546445189120 |
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| author | Zhang, Yuhan Wang, Zhou Shu, Zhou Zhou, Jiuren Xu, Yanqing Tang, Xiaonan Qiao, Shushan Ye, Tianchun Liu, Yang Bharath, Anil A. Drakakis, Emm Mic |
| author_facet | Zhang, Yuhan Wang, Zhou Shu, Zhou Zhou, Jiuren Xu, Yanqing Tang, Xiaonan Qiao, Shushan Ye, Tianchun Liu, Yang Bharath, Anil A. Drakakis, Emm Mic |
| contents | In recent years, DeepSeek has achieved strong inference performance but remains hard to deploy on energy-constrained edge devices. This paper presents the DeepSeek Processing Element (DSPE), an edge-oriented architecture that alleviates the model's heavy computational and energy demands. DSPE introduces three techniques: the MerkleTree-based Incremental Pruning Scheme (MIPS) for secure redundant-vector reduction, the Multi-Stage Boothing Lookup Method (MBLM) for bit-flip-aware approximate multiplication, and the Dynamic Adaptive Posit Processing Mechanism (DAPPM), which introduces a new DA-Posit format and its corresponding hardware multiplication architecture. Implemented in TSMC 28nm CMOS, DSPE achieves 109.4 TFLOPS/W energy efficiency compared with state-of-the-art designs and offers a scalable foundation for edge deployment. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_08615 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | DSPE: An Energy-Efficient Edge Processor for DeepSeek Inference with MerkleTree-based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing Zhang, Yuhan Wang, Zhou Shu, Zhou Zhou, Jiuren Xu, Yanqing Tang, Xiaonan Qiao, Shushan Ye, Tianchun Liu, Yang Bharath, Anil A. Drakakis, Emm Mic Hardware Architecture B.7.1; C.1.3 In recent years, DeepSeek has achieved strong inference performance but remains hard to deploy on energy-constrained edge devices. This paper presents the DeepSeek Processing Element (DSPE), an edge-oriented architecture that alleviates the model's heavy computational and energy demands. DSPE introduces three techniques: the MerkleTree-based Incremental Pruning Scheme (MIPS) for secure redundant-vector reduction, the Multi-Stage Boothing Lookup Method (MBLM) for bit-flip-aware approximate multiplication, and the Dynamic Adaptive Posit Processing Mechanism (DAPPM), which introduces a new DA-Posit format and its corresponding hardware multiplication architecture. Implemented in TSMC 28nm CMOS, DSPE achieves 109.4 TFLOPS/W energy efficiency compared with state-of-the-art designs and offers a scalable foundation for edge deployment. |
| title | DSPE: An Energy-Efficient Edge Processor for DeepSeek Inference with MerkleTree-based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing |
| topic | Hardware Architecture B.7.1; C.1.3 |
| url | https://arxiv.org/abs/2605.08615 |