Ke, C. (2026). Single 32-bit Sub-Channel DDR5 DIMMs: Architecture, Performance Bounds, and Standardisation.
Citazione stile Chigago Style (17a edizione)Ke, Chih-Hua. Single 32-bit Sub-Channel DDR5 DIMMs: Architecture, Performance Bounds, and Standardisation. 2026.
Citatione MLA (9a ed.)Ke, Chih-Hua. Single 32-bit Sub-Channel DDR5 DIMMs: Architecture, Performance Bounds, and Standardisation. 2026.
Attenzione: Queste citazioni potrebbero non essere precise al 100%.