APA (7th ed.) Citation

Ke, C. (2026). Single 32-bit Sub-Channel DDR5 DIMMs: Architecture, Performance Bounds, and Standardisation.

Chicago Style (17th ed.) Citation

Ke, Chih-Hua. Single 32-bit Sub-Channel DDR5 DIMMs: Architecture, Performance Bounds, and Standardisation. 2026.

MLA (9th ed.) Citation

Ke, Chih-Hua. Single 32-bit Sub-Channel DDR5 DIMMs: Architecture, Performance Bounds, and Standardisation. 2026.

Warning: These citations may not always be 100% accurate.