Breaking the scalability barrier via a vertical tunable coupler in 3D integrated transmon system
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arXiv
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| Autores principales: | , , , , , , , , , , , , , |
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| Formato: | Preprint |
| Publicado: |
2026
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| Materias: | |
| Acceso en línea: | |
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| _version_ | 1866916003724656640 |
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| author | Liao, Xudong Pan, Shuyi Zhang, Zhenxing Huai, Sainan Zong, Zhiwen Yang, Xiaopei Bu, Kunliang Zheng, Wen Tan, Xinsheng Yu, Yang Li, Yuan Zheng, Yi-Cong Cai, Tianqi Zhang, Shengyu |
| author_facet | Liao, Xudong Pan, Shuyi Zhang, Zhenxing Huai, Sainan Zong, Zhiwen Yang, Xiaopei Bu, Kunliang Zheng, Wen Tan, Xinsheng Yu, Yang Li, Yuan Zheng, Yi-Cong Cai, Tianqi Zhang, Shengyu |
| contents | Scaling superconducting quantum processors beyond the constraints of monolithic planar architectures is essential for fault-tolerant quantum computation. Here we demonstrate a three-dimensional (3D) integrated superconducting quantum processor in which two qubit chips are vertically stacked on opposing sides of a carrier chip and galvanically connected via multilayer flip-chip bonding. Intrachip qubit coupling is mediated by planar tunable couplers, whereas interchip coupling is enabled by vertical tunable couplers embedded in the carrier chip. Randomized benchmarking reveals simultaneous single-qubit gate fidelities of 99.87 % with negligible crosstalk, and controlled-Z gates achieve an average fidelity of 97.5 % for both intrachip and interchip operations. We further demonstrate high-fidelity Bell-state preparation and coherent generation of a four-qubit $W$ state, confirming the architecture's capability for interchip entanglement distribution. These results establish vertical coupling as a promising pathway toward scalable quantum processors compatible with advanced quantum error-correcting codes. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_11488 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Breaking the scalability barrier via a vertical tunable coupler in 3D integrated transmon system Liao, Xudong Pan, Shuyi Zhang, Zhenxing Huai, Sainan Zong, Zhiwen Yang, Xiaopei Bu, Kunliang Zheng, Wen Tan, Xinsheng Yu, Yang Li, Yuan Zheng, Yi-Cong Cai, Tianqi Zhang, Shengyu Quantum Physics Scaling superconducting quantum processors beyond the constraints of monolithic planar architectures is essential for fault-tolerant quantum computation. Here we demonstrate a three-dimensional (3D) integrated superconducting quantum processor in which two qubit chips are vertically stacked on opposing sides of a carrier chip and galvanically connected via multilayer flip-chip bonding. Intrachip qubit coupling is mediated by planar tunable couplers, whereas interchip coupling is enabled by vertical tunable couplers embedded in the carrier chip. Randomized benchmarking reveals simultaneous single-qubit gate fidelities of 99.87 % with negligible crosstalk, and controlled-Z gates achieve an average fidelity of 97.5 % for both intrachip and interchip operations. We further demonstrate high-fidelity Bell-state preparation and coherent generation of a four-qubit $W$ state, confirming the architecture's capability for interchip entanglement distribution. These results establish vertical coupling as a promising pathway toward scalable quantum processors compatible with advanced quantum error-correcting codes. |
| title | Breaking the scalability barrier via a vertical tunable coupler in 3D integrated transmon system |
| topic | Quantum Physics |
| url | https://arxiv.org/abs/2605.11488 |