Guardado en:
| Autores principales: | Hu, Yuting, Zhuang, Lei, Wang, Chen, Qin, Ruiyang, Xiang, Hua, Nam, Gi-joon, Xiong, Jinjun |
|---|---|
| Formato: | Preprint |
| Publicado: |
2026
|
| Materias: | |
| Acceso en línea: | https://arxiv.org/abs/2605.12528 |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
Ejemplares similares
Intelligent OPC Engineer Assistant for Semiconductor Manufacturing
por: Chen, Guojin, et al.
Publicado: (2024)
por: Chen, Guojin, et al.
Publicado: (2024)
Multi-Objective Optimization for Common-Centroid Placement of Analog Transistors
por: Maji, Supriyo, et al.
Publicado: (2024)
por: Maji, Supriyo, et al.
Publicado: (2024)
HiKonv: Maximizing the Throughput of Quantized Convolution With Novel Bit-wise Management and Computation
por: Chen, Yao, et al.
Publicado: (2022)
por: Chen, Yao, et al.
Publicado: (2022)
MASQ: Accelerating Masked Diffusion via Stage-Wise Multi-Precision Quantization
por: Kim, Seeyeon, et al.
Publicado: (2026)
por: Kim, Seeyeon, et al.
Publicado: (2026)
ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis
por: Li, Runkai, et al.
Publicado: (2025)
por: Li, Runkai, et al.
Publicado: (2025)
MaskOpt: A Large-Scale Mask Optimization Dataset to Advance AI in Integrated Circuit Manufacturing
por: Hu, Yuting, et al.
Publicado: (2025)
por: Hu, Yuting, et al.
Publicado: (2025)
IMMSched: Interruptible Multi-DNN Scheduling via Parallel Multi-Particle Optimizing Subgraph Isomorphism
por: Zhao, Boran, et al.
Publicado: (2026)
por: Zhao, Boran, et al.
Publicado: (2026)
Wit-HW: Bug Localization in Hardware Design Code via Witness Test Case Generation
por: Ma, Ruiyang, et al.
Publicado: (2025)
por: Ma, Ruiyang, et al.
Publicado: (2025)
Fleet: Hierarchical Task-based Abstraction for Megakernels on Multi-Die GPUs
por: Chowdhary, Sangeeta, et al.
Publicado: (2026)
por: Chowdhary, Sangeeta, et al.
Publicado: (2026)
UB-Mesh: a Hierarchically Localized nD-FullMesh Datacenter Network Architecture
por: Liao, Heng, et al.
Publicado: (2025)
por: Liao, Heng, et al.
Publicado: (2025)
Invited: Toward Accurate, Large-scale Electromigration Analysis and Optimization in Integrated Systems
por: Sapatnekar, Sachin S.
Publicado: (2026)
por: Sapatnekar, Sachin S.
Publicado: (2026)
HERO-Sign: Hierarchical Tuning and Efficient Compiler-Time GPU Optimizations for SPHINCS+ Signature Generation
por: Zhou, Yaoyun, et al.
Publicado: (2025)
por: Zhou, Yaoyun, et al.
Publicado: (2025)
Communication Characterization of AI Workloads for Large-scale Multi-chiplet Accelerators
por: Musavi, Mariam, et al.
Publicado: (2024)
por: Musavi, Mariam, et al.
Publicado: (2024)
TLX: Hardware-Native, Evolvable MIMW GPU Compiler for Large-scale Production Environments
por: Guan, Yue, et al.
Publicado: (2026)
por: Guan, Yue, et al.
Publicado: (2026)
CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval
por: Li, Xinzhao, et al.
Publicado: (2026)
por: Li, Xinzhao, et al.
Publicado: (2026)
RTLSquad: Multi-Agent Based Interpretable RTL Design
por: Wang, Bowei, et al.
Publicado: (2025)
por: Wang, Bowei, et al.
Publicado: (2025)
PIM-GPT: A Hybrid Process-in-Memory Accelerator for Autoregressive Transformers
por: Wu, Yuting, et al.
Publicado: (2023)
por: Wu, Yuting, et al.
Publicado: (2023)
LLM-Powered Code Analysis and Optimization for Gaussian Splatting Kernels
por: Hu, Yi, et al.
Publicado: (2025)
por: Hu, Yi, et al.
Publicado: (2025)
Fast Cross-Operator Optimization of Attention Dataflow
por: Chang, Haodong, et al.
Publicado: (2026)
por: Chang, Haodong, et al.
Publicado: (2026)
SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling
por: Wang, Huizheng, et al.
Publicado: (2024)
por: Wang, Huizheng, et al.
Publicado: (2024)
MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors
por: You, Dean, et al.
Publicado: (2025)
por: You, Dean, et al.
Publicado: (2025)
Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms
por: Colleman, Steven, et al.
Publicado: (2024)
por: Colleman, Steven, et al.
Publicado: (2024)
MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference
por: Kirschner, Maximilian, et al.
Publicado: (2025)
por: Kirschner, Maximilian, et al.
Publicado: (2025)
Mapping Space Exploration for Multi-Chiplet Accelerators Targeting LLM Inference Serving Workloads
por: Li, Boyu, et al.
Publicado: (2025)
por: Li, Boyu, et al.
Publicado: (2025)
SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
por: Li, Chengxi, et al.
Publicado: (2025)
por: Li, Chengxi, et al.
Publicado: (2025)
Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication
por: Riedel, Samuel, et al.
Publicado: (2025)
por: Riedel, Samuel, et al.
Publicado: (2025)
Special Session: Sustainable Deployment of Deep Neural Networks on Non-Volatile Compute-in-Memory Accelerators
por: Qin, Yifan, et al.
Publicado: (2025)
por: Qin, Yifan, et al.
Publicado: (2025)
RePart: Efficient Hypergraph Partitioning with Logic Replication Optimization for Multi-FPGA System
por: Fu, Zizhuo, et al.
Publicado: (2026)
por: Fu, Zizhuo, et al.
Publicado: (2026)
Optimized Memory System Architecture for VESA VDC-M Decoder with Multi-Slice Support
por: Yang, Hannah, et al.
Publicado: (2025)
por: Yang, Hannah, et al.
Publicado: (2025)
MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules
por: Raj, Ritik, et al.
Publicado: (2025)
por: Raj, Ritik, et al.
Publicado: (2025)
TEMP: A Memory Efficient Physical-aware Tensor Partition-Mapping Framework on Wafer-scale Chips
por: Wang, Huizheng, et al.
Publicado: (2025)
por: Wang, Huizheng, et al.
Publicado: (2025)
Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer
por: Hu, Xiangfei, et al.
Publicado: (2024)
por: Hu, Xiangfei, et al.
Publicado: (2024)
UbiMoE: A Ubiquitous Mixture-of-Experts Vision Transformer Accelerator With Hybrid Computation Pattern on FPGA
por: Dong, Jiale, et al.
Publicado: (2025)
por: Dong, Jiale, et al.
Publicado: (2025)
Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
por: Wang, Weiying, et al.
Publicado: (2026)
por: Wang, Weiying, et al.
Publicado: (2026)
DS2SC-Agent: A Multi-Agent Automated Pipeline for Rapid Chiplet Model Generation
por: Wu, Yiwei, et al.
Publicado: (2026)
por: Wu, Yiwei, et al.
Publicado: (2026)
Bridging the Gap between Hardware Fuzzing and Industrial Verification
por: Ma, Ruiyang, et al.
Publicado: (2025)
por: Ma, Ruiyang, et al.
Publicado: (2025)
RoMe: Row Granularity Access Memory System for Large Language Models
por: Nam, Hwayong, et al.
Publicado: (2025)
por: Nam, Hwayong, et al.
Publicado: (2025)
Automated HEMT Model Construction from Datasheets via Multi-Modal Intelligence and Prior-Knowledge-Free Optimization
por: Peng, Yuang, et al.
Publicado: (2025)
por: Peng, Yuang, et al.
Publicado: (2025)
AnalogMaster: Large Language Model-based Automated Analog IC Design Framework from Image to Layout
por: Qin, Xian Rong, et al.
Publicado: (2026)
por: Qin, Xian Rong, et al.
Publicado: (2026)
Advancing Assistive Robotics: Multi-Modal Navigation and Biophysical Monitoring for Next-Generation Wheelchairs
por: Hossain, Md. Anowar, et al.
Publicado: (2026)
por: Hossain, Md. Anowar, et al.
Publicado: (2026)
Ejemplares similares
-
Intelligent OPC Engineer Assistant for Semiconductor Manufacturing
por: Chen, Guojin, et al.
Publicado: (2024) -
Multi-Objective Optimization for Common-Centroid Placement of Analog Transistors
por: Maji, Supriyo, et al.
Publicado: (2024) -
HiKonv: Maximizing the Throughput of Quantized Convolution With Novel Bit-wise Management and Computation
por: Chen, Yao, et al.
Publicado: (2022) -
MASQ: Accelerating Masked Diffusion via Stage-Wise Multi-Precision Quantization
por: Kim, Seeyeon, et al.
Publicado: (2026) -
ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis
por: Li, Runkai, et al.
Publicado: (2025)