Cover Image

Reward-Weighted On-Policy Distillation with an Open Property-Equivalence Verifier for NL-to-SVA Generation

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Zou, Qingyun, Li, Yingze, Liu, Tianen, He, Bingsheng, Wong, Weng-Fai
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture Machine Learning
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Is Agentic AI Ready for Real-World Hardware Engineering? A Deep Dive with Phoenix-bench
by: Zou, Qingyun, et al.
Published: (2026)

HLStrans: Dataset for C-to-HLS Hardware Code Synthesis
by: Zou, Qingyun, et al.
Published: (2025)

XtraMAC: An Efficient MAC Architecture for Mixed-Precision LLM Inference on FPGA
by: Yu, Feng, et al.
Published: (2026)

Automated SVA Generation with LLMs
by: Fu, Lik Tung, et al.
Published: (2026)

Binary Weight Multi-Bit Activation Quantization for Compute-in-Memory CNN Accelerators
by: Zhou, Wenyong, et al.
Published: (2025)

RidgeWalker: Perfectly Pipelined Graph Random Walks on FPGAs
by: Tan, Hongshi, et al.
Published: (2026)

ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
by: Fu, Lik Tung, et al.
Published: (2026)

Circuit Transformer: A Transformer That Preserves Logical Equivalence
by: Li, Xihan, et al.
Published: (2024)

SparrowSNN: A Hardware/software Co-design for Energy Efficient ECG Classification
by: Yan, Zhanglu, et al.
Published: (2024)

QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis
by: Wu, Yutong, et al.
Published: (2026)

U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators
by: Yan, Zheyu, et al.
Published: (2023)

NOVA: NoC-based Vector Unit for Mapping Attention Layers on a CNN Accelerator
by: Upadhyay, Mohit, et al.
Published: (2024)

OpenACMv2: An Accuracy-Constrained Co-Optimization Framework for Approximate DCiM
by: Zhou, Yiqi, et al.
Published: (2026)

Federated Knowledge Distillation for Multi-Model Architectures Lithography Hotspot Detection
by: Li, Yuqi, et al.
Published: (2025)

Layer-wise Weight Selection for Power-Efficient Neural Network Acceleration
by: Fang, Jiaxun, et al.
Published: (2025)

PaCKD: Pattern-Clustered Knowledge Distillation for Compressing Memory Access Prediction Models
by: Gupta, Neelesh, et al.
Published: (2024)

Architectural Implications of Neural Network Inference for High Data-Rate, Low-Latency Scientific Applications
by: Weng, Olivia, et al.
Published: (2024)

FGMP: Fine-Grained Mixed-Precision Weight and Activation Quantization for Hardware-Accelerated LLM Inference
by: Hooper, Coleman, et al.
Published: (2025)

A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface
by: Yin, Guodong, et al.
Published: (2022)

AiEDA: An Open-Source AI-Aided Design Library for Design-to-Vector
by: Qiu, Yihang, et al.
Published: (2025)

SiHGNN: Leveraging Properties of Semantic Graphs for Efficient HGNN Acceleration
by: Xue, Runzhen, et al.
Published: (2024)

ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
by: Su, Zhe, et al.
Published: (2025)

FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols
by: Shih, Yu-An, et al.
Published: (2025)

M100: An Orchestrated Dataflow Architecture Powering General AI Computing
by: Xie, Yan, et al.
Published: (2026)

GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
by: Fang, Wenji, et al.
Published: (2025)

A2Q+: Improving Accumulator-Aware Weight Quantization
by: Colbert, Ian, et al.
Published: (2024)

CuAsmRL: Optimizing GPU SASS Schedules via Deep Reinforcement Learning
by: He, Guoliang, et al.
Published: (2025)

PowerGenie: Analytically-Guided Evolutionary Discovery of Superior Reconfigurable Power Converters
by: Gao, Jian, et al.
Published: (2026)

LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models
by: Thorat, Kiran, et al.
Published: (2025)

Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
by: Pinckney, Nathaniel, et al.
Published: (2025)

Exploring the Agentic Frontier of Verilog Code Generation
by: Yubeaton, Patrick, et al.
Published: (2026)

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs
by: He, Zifan, et al.
Published: (2025)

Algorithm and Hardware Co-Design for Efficient Complex-Valued Uncertainty Estimation
by: Zhang, Zehuan, et al.
Published: (2026)

DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference
by: Sonnino, Lorenzo, et al.
Published: (2023)

DS-CIM: Digital Stochastic Computing-In-Memory Featuring Accurate OR-Accumulation via Sample Region Remapping for Edge AI Models
by: Shao, Kunming, et al.
Published: (2026)

Accelerating Diffusion Models for Generative AI Applications with Silicon Photonics
by: Suresh, Tharini, et al.
Published: (2026)

MAGE: A Multi-Agent Engine for Automated RTL Code Generation
by: Zhao, Yujie, et al.
Published: (2024)

GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification
by: Pham, Phuoc, et al.
Published: (2025)

PhotoGAN: Generative Adversarial Neural Network Acceleration with Silicon Photonics
by: Suresh, Tharini, et al.
Published: (2025)

On Robustness and Generalization of ML-Based Congestion Predictors to Valid and Imperceptible Perturbations
by: Holtz, Chester, et al.
Published: (2024)