:: Library Catalog

Cover Image

Saved in:

Bibliographic Details
Main Authors:	Biel, Sascha, Gaede, Carl Alexander, Glaser, Amiel, Wolter, Jan, Schelle, Alexej
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture Artificial Intelligence Computational Engineering, Finance, and Science
Online Access:	https://arxiv.org/abs/2605.15212
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design
by: Mehradfar, Asal, et al.
Published: (2025)

HDLdebugger: Streamlining HDL debugging with Large Language Models
by: Yao, Xufeng, et al.
Published: (2024)

NoX: a Compact Open-Source RISC-V Processor for Multi-Processor Systems-on-Chip
by: Silva, Anderson I., et al.
Published: (2024)

On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures
by: Elahi, Mehdi, et al.
Published: (2025)

Stochastic Nonlinear Dynamical Modelling of SRAM Bitcells in Retention Mode
by: Van Brandt, Léopold, et al.
Published: (2024)

A Lightweight Inception Boosted U-Net Neural Network for Routability Prediction
by: Li, Hailiang, et al.
Published: (2024)

DRCY: Agentic Hardware Design Reviews
by: Dumont, Kyle, et al.
Published: (2026)

ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development
by: Wang, Bowei, et al.
Published: (2025)

Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation
by: Liu, Jiale, et al.
Published: (2026)

HW/SW Co-design of a PCM/PWM converter: a System Level Approach based in the SpecC Methodology
by: Petrini, Daniel G. P., et al.
Published: (2025)

DUET: Agentic Design Understanding via Experimentation and Testing
by: Smith, Gus Henry, et al.
Published: (2025)

Is Agentic AI Ready for Real-World Hardware Engineering? A Deep Dive with Phoenix-bench
by: Zou, Qingyun, et al.
Published: (2026)

FVRuleLearner: Operator-Level Reasoning Tree (OP-Tree)-Based Rules Learning for Formal Verification
by: Wan, Lily Jiaxin, et al.
Published: (2026)

RTLSquad: Multi-Agent Based Interpretable RTL Design
by: Wang, Bowei, et al.
Published: (2025)

A Semi-Formal Verification Methodology for Efficient Configuration Coverage of Highly Configurable Digital Designs
by: Kumar, Aman, et al.
Published: (2024)

RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
by: Yao, Xufeng, et al.
Published: (2024)

AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models
by: Zhang, Haoyi, et al.
Published: (2024)

The Cream Rises to the Top: Efficient Reranking Method for Verilog Code Generation
by: Yang, Guang, et al.
Published: (2025)

VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
by: Wang, Ning, et al.
Published: (2025)

FuzzWiz -- Fuzzing Framework for Efficient Hardware Coverage
by: Gadde, Deepak Narayan, et al.
Published: (2024)

IncreRTL: Traceability-Guided Incremental RTL Generation under Requirement Evolution
by: Chen, Luanrong, et al.
Published: (2026)

Emerging ML-AI Techniques for Analog and RF EDA
by: Wu, Zhengfeng, et al.
Published: (2025)

Post-Moore Technologies for Plasma Simulation: A Community Roadmap
by: Pennati, Luca, et al.
Published: (2026)

A low-rank balanced truncation approach for large-scale RLCk model order reduction based on extended Krylov subspace and a frequency-aware convergence criterion
by: Giamouzis, Christos, et al.
Published: (2024)

EncodingNet: A Novel Encoding-based MAC Design for Efficient Neural Network Acceleration
by: Liu, Bo, et al.
Published: (2024)

MORCIC: Model Order Reduction Techniques for Electromagnetic Models of Integrated Circuits
by: Garyfallou, Dimitrios, et al.
Published: (2023)

Advanced Integration Strategies for ESD Protection and Termination in High-Speed LVDS Systems
by: Gaddipati, Kavya
Published: (2025)

Energy-Efficient Ternary Encoding for High-Speed Data Transmission in 3D-Integrated Circuits Using Inductive Coupling Links
by: Alghotmi, Abdullah Saeed
Published: (2025)

QuArch: A Benchmark for Evaluating LLM Reasoning in Computer Architecture
by: Prakash, Shvetank, et al.
Published: (2025)

Monitor Placement for Fault Localization in Deep Neural Network Accelerators
by: Liu, Wei-Kai
Published: (2023)

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation
by: Chang, Kaiyan, et al.
Published: (2024)

Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generation
by: Khan, M Zafir Sadik, et al.
Published: (2026)

Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors
by: Dupuis, Nicolas, et al.
Published: (2025)

LM-Fix: Lightweight Bit-Flip Detection and Rapid Recovery Framework for Language Models
by: Tahmasivand, Ahmad, et al.
Published: (2025)

David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
by: Shankar, Shashwat, et al.
Published: (2025)

LLM-aided explanations of EDA synthesis errors
by: Qiu, Siyu, et al.
Published: (2024)

A Survey: Collaborative Hardware and Software Design in the Era of Large Language Models
by: Guo, Cong, et al.
Published: (2024)

UCAgent: An End-to-End Agent for Block-Level Functional Verification
by: Wang, Junyue, et al.
Published: (2026)

A Micro Architectural Events Aware Real-Time Embedded System Fault Injector
by: Magliano, Enrico, et al.
Published: (2024)

Row-Column Hybrid Grouping for Fault-Resilient Multi-Bit Weight Representation on IMC Arrays
by: Jeon, Kang Eun, et al.
Published: (2025)