ITHICA: Intra-Thread Instruction Checking Approach for Defect-Induced Silent Data Corruptions
Fuente:
arXiv
Saved in:
| Main Authors: | Vavelidou, Ioanna, Banerjee, Subho S., Liu, Eric X., Fuller, Mike, Mitra, Subhasish, Trippel, Caroline |
|---|---|
| Format: | Preprint |
| Published: |
2026
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Silent Data Corruption by 10x Test Escapes Threatens Reliable Computing
by: Mitra, Subhasish, et al.
Published: (2025)
by: Mitra, Subhasish, et al.
Published: (2025)
EquivFusion: Unifying Hardware Equivalence Checking from Algorithms to Netlists via MLIR
by: Zhu, Jiaying, et al.
Published: (2026)
by: Zhu, Jiaying, et al.
Published: (2026)
LeGend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking
by: Miao, Mingkai, et al.
Published: (2026)
by: Miao, Mingkai, et al.
Published: (2026)
The Anatomy of Silent Data Corruption: GPU Error Pattern Study and Modeling Guidance
by: Tung, Chung-Hsuan, et al.
Published: (2026)
by: Tung, Chung-Hsuan, et al.
Published: (2026)
On the Vulnerability of FHE Computation to Silent Data Corruption
by: Mu, Jianan, et al.
Published: (2026)
by: Mu, Jianan, et al.
Published: (2026)
VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation
by: Wei, Anjiang, et al.
Published: (2025)
by: Wei, Anjiang, et al.
Published: (2025)
Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
by: Armato, Antonino, et al.
Published: (2026)
by: Armato, Antonino, et al.
Published: (2026)
LLM-PRISM: Characterizing Silent Data Corruption from Permanent GPU Faults in LLM Training
by: Tyagi, Abhishek, et al.
Published: (2026)
by: Tyagi, Abhishek, et al.
Published: (2026)
Analyzing and Exploiting Branch Mispredictions in Microcode
by: Mosier, Nicholas, et al.
Published: (2025)
by: Mosier, Nicholas, et al.
Published: (2025)
FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols
by: Shih, Yu-An, et al.
Published: (2025)
by: Shih, Yu-An, et al.
Published: (2025)
Using LLMs to Facilitate Formal Verification of RTL
by: Orenes-Vera, Marcelo, et al.
Published: (2023)
by: Orenes-Vera, Marcelo, et al.
Published: (2023)
Hardware-Accelerated Algorithm for Complex Function Roots Density Graph Plotting
by: Tang, Ruibai, et al.
Published: (2025)
by: Tang, Ruibai, et al.
Published: (2025)
Offloading Data Center Tax
by: Revankar, Akshay, et al.
Published: (2025)
by: Revankar, Akshay, et al.
Published: (2025)
Inexactness and Correction of Floating-Point Reciprocal, Division and Square Root
by: Dutton, Lucas M., et al.
Published: (2024)
by: Dutton, Lucas M., et al.
Published: (2024)
UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
by: Ye, Junhao, et al.
Published: (2026)
by: Ye, Junhao, et al.
Published: (2026)
SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers
by: Scheffler, Paul, et al.
Published: (2024)
by: Scheffler, Paul, et al.
Published: (2024)
MEIC: Re-thinking RTL Debug Automation using LLMs
by: Xu, Ke, et al.
Published: (2024)
by: Xu, Ke, et al.
Published: (2024)
AutoINV: Automated Invariant Generation Framework for Formal Verification on High-Level Synthesis Designs
by: Zhou, Xiaofeng, et al.
Published: (2026)
by: Zhou, Xiaofeng, et al.
Published: (2026)
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
by: Collini, Luca, et al.
Published: (2024)
by: Collini, Luca, et al.
Published: (2024)
FormalRTL: Verified RTL Synthesis at Scale
by: Li, Kezhi, et al.
Published: (2026)
by: Li, Kezhi, et al.
Published: (2026)
A Vertically Integrated Framework for Templatized Chip Design
by: Kim, Jeongeun, et al.
Published: (2025)
by: Kim, Jeongeun, et al.
Published: (2025)
A Novel HDL Code Generator for Effectively Testing FPGA Logic Synthesis Compilers
by: Xu, Zhihao, et al.
Published: (2024)
by: Xu, Zhihao, et al.
Published: (2024)
Structural Mutation Based Differential Testing for FPGA Logic Synthesis Compilers
by: Xu, Zhihao, et al.
Published: (2025)
by: Xu, Zhihao, et al.
Published: (2025)
Scalable Software Testing in Fast Virtual Platforms: Leveraging SystemC, QEMU and Containerization
by: Jünger, Lukas, et al.
Published: (2025)
by: Jünger, Lukas, et al.
Published: (2025)
Generalized Methodology for Determining Numerical Features of Hardware Floating-Point Matrix Multipliers: Part I
by: Khattak, Faizan A, et al.
Published: (2025)
by: Khattak, Faizan A, et al.
Published: (2025)
CounterPoint: Using Hardware Event Counters to Refute and Refine Microarchitectural Assumptions (Extended Version)
by: Lindsay, Nick, et al.
Published: (2026)
by: Lindsay, Nick, et al.
Published: (2026)
The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages
by: Schreiner, Johannes, et al.
Published: (2024)
by: Schreiner, Johannes, et al.
Published: (2024)
HW/SW Co-design of a PCM/PWM converter: a System Level Approach based in the SpecC Methodology
by: Petrini, Daniel G. P., et al.
Published: (2025)
by: Petrini, Daniel G. P., et al.
Published: (2025)
Revet: A Language and Compiler for Dataflow Threads
by: Rucker, Alexander, et al.
Published: (2023)
by: Rucker, Alexander, et al.
Published: (2023)
GreenMalloc: Allocator Optimisation for Industrial Workloads
by: Dakhama, Aidan, et al.
Published: (2025)
by: Dakhama, Aidan, et al.
Published: (2025)
DGEMM without FP64 Arithmetic - Using FP64 Emulation and FP8 Tensor Cores with Ozaki Scheme
by: Mukunoki, Daichi
Published: (2025)
by: Mukunoki, Daichi
Published: (2025)
Bridging the Gap: Physical PCI Device Integration Into SystemC-TLM Virtual Platforms
by: Bosbach, Nils, et al.
Published: (2025)
by: Bosbach, Nils, et al.
Published: (2025)
Selective Parallel Loading of Large-Scale Compressed Graphs with ParaGrapher
by: Esfahani, Mohsen Koohi, et al.
Published: (2024)
by: Esfahani, Mohsen Koohi, et al.
Published: (2024)
The Future of Memory: Limits and Opportunities
by: Dayo, Samuel, et al.
Published: (2025)
by: Dayo, Samuel, et al.
Published: (2025)
Beyond Static Policies: Exploring Dynamic Policy Selection for Single-Thread Performance Optimization
by: Zhang, Yanxin, et al.
Published: (2026)
by: Zhang, Yanxin, et al.
Published: (2026)
DRCY: Agentic Hardware Design Reviews
by: Dumont, Kyle, et al.
Published: (2026)
by: Dumont, Kyle, et al.
Published: (2026)
ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development
by: Wang, Bowei, et al.
Published: (2025)
by: Wang, Bowei, et al.
Published: (2025)
Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation
by: Liu, Jiale, et al.
Published: (2026)
by: Liu, Jiale, et al.
Published: (2026)
A High-level Synthesis Toolchain for the Julia Language
by: Short, Benedict, et al.
Published: (2025)
by: Short, Benedict, et al.
Published: (2025)
DUET: Agentic Design Understanding via Experimentation and Testing
by: Smith, Gus Henry, et al.
Published: (2025)
by: Smith, Gus Henry, et al.
Published: (2025)
Similar Items
-
Silent Data Corruption by 10x Test Escapes Threatens Reliable Computing
by: Mitra, Subhasish, et al.
Published: (2025) -
EquivFusion: Unifying Hardware Equivalence Checking from Algorithms to Netlists via MLIR
by: Zhu, Jiaying, et al.
Published: (2026) -
LeGend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking
by: Miao, Mingkai, et al.
Published: (2026) -
The Anatomy of Silent Data Corruption: GPU Error Pattern Study and Modeling Guidance
by: Tung, Chung-Hsuan, et al.
Published: (2026) -
On the Vulnerability of FHE Computation to Silent Data Corruption
by: Mu, Jianan, et al.
Published: (2026)