ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses
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arXiv
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| Format: | Preprint |
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2026
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| _version_ | 1866916015636480000 |
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| author | Li, Mengming Miao, Chenlu Xu, Buqing Zhang, Qijun Sun, Xiangfeng Xu, Ceyu Xie, Yuan Li, Wenkai Liu, Shang Xie, Zhiyao |
| author_facet | Li, Mengming Miao, Chenlu Xu, Buqing Zhang, Qijun Sun, Xiangfeng Xu, Ceyu Xie, Yuan Li, Wenkai Liu, Shang Xie, Zhiyao |
| contents | Irregular memory accesses pose challenges for effective and efficient data prefetching. While temporal prefetchers have recently shown promise for irregular memory access patterns, their effectiveness fundamentally depends on temporal address recurrence and large metadata storage. When memory addresses exhibit weak or no recurrence, as in indirect memory accesses, temporal prefetchers achieve limited performance gains while incurring substantial storage overhead.
This paper proposes Instruction-Correlation Prefetching (ICP), a new hardware prefetching mechanism that exploits instruction-level correlations rather than memory-address correlations to handle irregular memory accesses. ICP observes that although memory addresses may not repeat, the instructions generating them often recur with stable data-dependency relationships. By learning these persistent instruction correlations, ICP speculatively computes and prefetches future irregular accesses using the execution results of their correlated predecessors. Across irregular SPEC CPU and GAP benchmarks, ICP outperforms the state-of-the-art temporal prefetcher Triangel by 14.0% and the indirect prefetcher DMP by 6.0%, while requiring only 2.1 KB of hardware storage, over three orders of magnitude smaller than temporal prefetchers. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_15645 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses Li, Mengming Miao, Chenlu Xu, Buqing Zhang, Qijun Sun, Xiangfeng Xu, Ceyu Xie, Yuan Li, Wenkai Liu, Shang Xie, Zhiyao Hardware Architecture Irregular memory accesses pose challenges for effective and efficient data prefetching. While temporal prefetchers have recently shown promise for irregular memory access patterns, their effectiveness fundamentally depends on temporal address recurrence and large metadata storage. When memory addresses exhibit weak or no recurrence, as in indirect memory accesses, temporal prefetchers achieve limited performance gains while incurring substantial storage overhead. This paper proposes Instruction-Correlation Prefetching (ICP), a new hardware prefetching mechanism that exploits instruction-level correlations rather than memory-address correlations to handle irregular memory accesses. ICP observes that although memory addresses may not repeat, the instructions generating them often recur with stable data-dependency relationships. By learning these persistent instruction correlations, ICP speculatively computes and prefetches future irregular accesses using the execution results of their correlated predecessors. Across irregular SPEC CPU and GAP benchmarks, ICP outperforms the state-of-the-art temporal prefetcher Triangel by 14.0% and the indirect prefetcher DMP by 6.0%, while requiring only 2.1 KB of hardware storage, over three orders of magnitude smaller than temporal prefetchers. |
| title | ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2605.15645 |