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| Main Authors: | , , , |
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| Format: | Preprint |
| Published: |
2026
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2605.15832 |
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| _version_ | 1866917499868545024 |
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| author | Aubach, Júlia Orteu Banchelli, Fabio Ramírez, Marc Clascà Garcia-Gasulla, Marta |
| author_facet | Aubach, Júlia Orteu Banchelli, Fabio Ramírez, Marc Clascà Garcia-Gasulla, Marta |
| contents | This work extends a framework for predicting the performance of High-Performance Computing (HPC) workloads using Machine Learning (ML). A common limitation in performance modeling is the restricted number of hardware counters that can be collected simultaneously. To address this, we propose a heuristic-based methodology to merge execution traces from multiple runs, each instrumented with a different set of hardware counters. Our approach matches computation bursts across executions by analyzing MPI structure, timing, and communication patterns. This process enables the construction of a unified dataset that includes a wider set of hardware features without relying on multiplexing. The output is a new synthetic trace with all merged counters, which can be used both for HPC performance prediction and for conventional performance analysis. The methodology has been validated on MareNostrum5 machine with a range of kernels and real applications. Results show that the merged counters maintain acceptable accuracy depending on the application, and can be directly used to train ML models on a richer feature space without prior counter selection. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_15832 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Heuristic-Based Merging of HPC Traces to Extend Hardware Counter Coverage Aubach, Júlia Orteu Banchelli, Fabio Ramírez, Marc Clascà Garcia-Gasulla, Marta Performance Machine Learning This work extends a framework for predicting the performance of High-Performance Computing (HPC) workloads using Machine Learning (ML). A common limitation in performance modeling is the restricted number of hardware counters that can be collected simultaneously. To address this, we propose a heuristic-based methodology to merge execution traces from multiple runs, each instrumented with a different set of hardware counters. Our approach matches computation bursts across executions by analyzing MPI structure, timing, and communication patterns. This process enables the construction of a unified dataset that includes a wider set of hardware features without relying on multiplexing. The output is a new synthetic trace with all merged counters, which can be used both for HPC performance prediction and for conventional performance analysis. The methodology has been validated on MareNostrum5 machine with a range of kernels and real applications. Results show that the merged counters maintain acceptable accuracy depending on the application, and can be directly used to train ML models on a richer feature space without prior counter selection. |
| title | Heuristic-Based Merging of HPC Traces to Extend Hardware Counter Coverage |
| topic | Performance Machine Learning |
| url | https://arxiv.org/abs/2605.15832 |