ADS-IMC: Accelerating Data Sorting with In-Memory Computation
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arXiv
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| Natura: | Preprint |
| Pubblicazione: |
2026
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| _version_ | 1866918504524939264 |
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| author | Dhakad, Narendra Singh Vishvakarma, Santosh Kumar |
| author_facet | Dhakad, Narendra Singh Vishvakarma, Santosh Kumar |
| contents | Sorting is a fundamental operation across numerous computational domains. Traditionally, this process involves transferring data from main memory to a processing unit for sorting, followed by writing the sorted data back to memory. This conventional approach incurs substantial latency and energy overheads due to the extensive data movement between memory and processing components. To mitigate these overheads, this paper introduces novel architectures for executing sorting operations directly within the memory fabric, eliminating the need for off-chip data transfer. To our knowledge, this work represents the first exploration of in-memory sorting using 6T SRAM. The proposed architecture is designed to operate on data represented in the standard weighted binary radix format commonly used in digital systems. The proposed architecture achieves a significant 3.4x reduction in latency compared to memristor-based IMC sorting. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_16213 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | ADS-IMC: Accelerating Data Sorting with In-Memory Computation Dhakad, Narendra Singh Vishvakarma, Santosh Kumar Hardware Architecture Sorting is a fundamental operation across numerous computational domains. Traditionally, this process involves transferring data from main memory to a processing unit for sorting, followed by writing the sorted data back to memory. This conventional approach incurs substantial latency and energy overheads due to the extensive data movement between memory and processing components. To mitigate these overheads, this paper introduces novel architectures for executing sorting operations directly within the memory fabric, eliminating the need for off-chip data transfer. To our knowledge, this work represents the first exploration of in-memory sorting using 6T SRAM. The proposed architecture is designed to operate on data represented in the standard weighted binary radix format commonly used in digital systems. The proposed architecture achieves a significant 3.4x reduction in latency compared to memristor-based IMC sorting. |
| title | ADS-IMC: Accelerating Data Sorting with In-Memory Computation |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2605.16213 |