Predictive Software Scheduling as an Early-Warning Hint Layer for Optical Engine Thermal Drift in Heterogeneous SoIC Packaging
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arXiv
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| Formato: | Preprint |
| Publicado: |
2026
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| _version_ | 1866916042166501376 |
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| author | Chung, Chi Fei |
| author_facet | Chung, Chi Fei |
| contents | As semiconductor scaling reaches the A16 / 2 nm node, the integration of co-packaged optics (CPO) via TSMC's Co-Packaged Optics Ultra Engine (COUPE) architecture introduces critical thermal-optical coupling challenges. Micro-ring resonators embedded in the Photonic Integrated Circuit (PIC) layer are exquisitely sensitive to temperature: a deviation of merely +-1.7 nm in resonant wavelength causes measurable Bit Error Rate (BER) degradation. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_18612 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Predictive Software Scheduling as an Early-Warning Hint Layer for Optical Engine Thermal Drift in Heterogeneous SoIC Packaging Chung, Chi Fei Hardware Architecture As semiconductor scaling reaches the A16 / 2 nm node, the integration of co-packaged optics (CPO) via TSMC's Co-Packaged Optics Ultra Engine (COUPE) architecture introduces critical thermal-optical coupling challenges. Micro-ring resonators embedded in the Photonic Integrated Circuit (PIC) layer are exquisitely sensitive to temperature: a deviation of merely +-1.7 nm in resonant wavelength causes measurable Bit Error Rate (BER) degradation. |
| title | Predictive Software Scheduling as an Early-Warning Hint Layer for Optical Engine Thermal Drift in Heterogeneous SoIC Packaging |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2605.18612 |