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A complete discussion on fully reconfigurable, digital, scalable, graph and sparsity-aware near-memory accelerator for graph neural networks

Fuente: arXiv

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Detalles Bibliográficos
Autores principales:	Raman, Siddhartha Raman Sundara, John, Lizy, Kulkarni, Jaydeep P.
Formato:	Preprint
Publicado:	2026
Materias:	Hardware Architecture
Acceso en línea:	Acceder al recurso
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

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