A Hardware-Based Multi-Stage Dynamic Power Management Architecture for Autonomous Low-Light Operation
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arXiv
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| Format: | Preprint |
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2026
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| author | Kouzinopoulos, Charalampos S. Meli, Marcel L. Schellenberg, Martin Poole, Philip J. Bellanger, Mathieu Kauer, Matthias De Vos, Julien Ioannidis, Dimosthenis Tzovaras, Dimitrios |
| author_facet | Kouzinopoulos, Charalampos S. Meli, Marcel L. Schellenberg, Martin Poole, Philip J. Bellanger, Mathieu Kauer, Matthias De Vos, Julien Ioannidis, Dimosthenis Tzovaras, Dimitrios |
| contents | The advance of autonomous Smart Sensor Networks and embedded systems for the Internet of Things, powered by photovoltaic energy harvesting, is severely limited by energy efficiency, especially in low-light environments. While Dynamic Power Management is essential for energy conservation, conventional software-based techniques that rely on processor-managed low-power states incur a persistent quiescent current drain. This current becomes the dominant energy sink in energy-scarce conditions, limiting autonomy. The work of this paper addresses this limitation by introducing a robust, hardware-orchestrated dynamic power management architecture that improves existing configurations for battery-based sensor nodes. The proposed architecture achieves a minimal quiescent drain of 452nA, by completely power-gating the microcontroller and all non-essential peripherals, with wake-up orchestrated by an ultra-low-power PMIC, RTC and a novel latch circuit developed specifically for this work. Our evaluation demonstrates that the dynamic power management architecture is significantly more efficient than traditional software-based sleep modes. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_19879 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | A Hardware-Based Multi-Stage Dynamic Power Management Architecture for Autonomous Low-Light Operation Kouzinopoulos, Charalampos S. Meli, Marcel L. Schellenberg, Martin Poole, Philip J. Bellanger, Mathieu Kauer, Matthias De Vos, Julien Ioannidis, Dimosthenis Tzovaras, Dimitrios Hardware Architecture B.7; B.8 The advance of autonomous Smart Sensor Networks and embedded systems for the Internet of Things, powered by photovoltaic energy harvesting, is severely limited by energy efficiency, especially in low-light environments. While Dynamic Power Management is essential for energy conservation, conventional software-based techniques that rely on processor-managed low-power states incur a persistent quiescent current drain. This current becomes the dominant energy sink in energy-scarce conditions, limiting autonomy. The work of this paper addresses this limitation by introducing a robust, hardware-orchestrated dynamic power management architecture that improves existing configurations for battery-based sensor nodes. The proposed architecture achieves a minimal quiescent drain of 452nA, by completely power-gating the microcontroller and all non-essential peripherals, with wake-up orchestrated by an ultra-low-power PMIC, RTC and a novel latch circuit developed specifically for this work. Our evaluation demonstrates that the dynamic power management architecture is significantly more efficient than traditional software-based sleep modes. |
| title | A Hardware-Based Multi-Stage Dynamic Power Management Architecture for Autonomous Low-Light Operation |
| topic | Hardware Architecture B.7; B.8 |
| url | https://arxiv.org/abs/2605.19879 |