Taking Cryptography Out of the Data Path via Near-Memory Processing in DRAM
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2026
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| _version_ | 1866913146514440192 |
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| author | Barcarolo, Nicola Gandham, Brahmaiah Sadrosadati, Mohammad Passerone, Roberto Mutlu, Onur Vella, Flavio |
| author_facet | Barcarolo, Nicola Gandham, Brahmaiah Sadrosadati, Mohammad Passerone, Roberto Mutlu, Onur Vella, Flavio |
| contents | Cryptographic algorithms such as AES-128 and SHA-256 are fundamental to ensuring data security and integrity. Although these algorithms are computationally efficient, their performance is often constrained by the processor-centric architectures (e.g., CPUs, GPUs), primarily due to the memory bottleneck. This constraint leads to increased latency and higher energy consumption, particularly when handling large volumes of data. To overcome these challenges, Processing-in-Memory (PIM) has emerged as a promising architectural paradigm, allowing computation to occur directly within or near memory units. By minimizing data movement between the processor and memory units, PIM can significantly accelerate cryptographic algorithms while improving energy efficiency. Several pieces of prior work have demonstrated the effectiveness of PIM at fundamentally accelerating cryptographic algorithms. However, none of the prior works have extensively demonstrated the potential of a real-world PIM system. In this paper, we want to investigate the potential and limitations of real-world PIM in accelerating cryptographic algorithms. As part of our methodology, the UPMEM PIM architecture is used to assess the scalability of cryptographic algorithms. When these algorithms operate on a single rank, their performance remains below that of modern CPUs. However, distributing the computation across multiple ranks significantly enhances performance. When all available ranks are utilized, real-world PIM can accelerate cryptographic algorithms more effectively. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_20047 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Taking Cryptography Out of the Data Path via Near-Memory Processing in DRAM Barcarolo, Nicola Gandham, Brahmaiah Sadrosadati, Mohammad Passerone, Roberto Mutlu, Onur Vella, Flavio Cryptography and Security Hardware Architecture Distributed, Parallel, and Cluster Computing Cryptographic algorithms such as AES-128 and SHA-256 are fundamental to ensuring data security and integrity. Although these algorithms are computationally efficient, their performance is often constrained by the processor-centric architectures (e.g., CPUs, GPUs), primarily due to the memory bottleneck. This constraint leads to increased latency and higher energy consumption, particularly when handling large volumes of data. To overcome these challenges, Processing-in-Memory (PIM) has emerged as a promising architectural paradigm, allowing computation to occur directly within or near memory units. By minimizing data movement between the processor and memory units, PIM can significantly accelerate cryptographic algorithms while improving energy efficiency. Several pieces of prior work have demonstrated the effectiveness of PIM at fundamentally accelerating cryptographic algorithms. However, none of the prior works have extensively demonstrated the potential of a real-world PIM system. In this paper, we want to investigate the potential and limitations of real-world PIM in accelerating cryptographic algorithms. As part of our methodology, the UPMEM PIM architecture is used to assess the scalability of cryptographic algorithms. When these algorithms operate on a single rank, their performance remains below that of modern CPUs. However, distributing the computation across multiple ranks significantly enhances performance. When all available ranks are utilized, real-world PIM can accelerate cryptographic algorithms more effectively. |
| title | Taking Cryptography Out of the Data Path via Near-Memory Processing in DRAM |
| topic | Cryptography and Security Hardware Architecture Distributed, Parallel, and Cluster Computing |
| url | https://arxiv.org/abs/2605.20047 |