SpecAlign: A Semantic Alignment Framework for SystemVerilog Assertion Generation
Fuente:
arXiv
Guardado en:
| Autores principales: | Imperial, Jaime Rafael, Zheng, Hao |
|---|---|
| Formato: | Preprint |
| Publicado: |
2026
|
| Materias: | |
| Acceso en línea: | |
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