Architectural Limits of Cloud TPUs in Finite-Field Cryptography
Fuente:
arXiv
Saved in:
| Main Authors: | Dang, Hung, Dang, Xuan Phu, Nguyen, Tue |
|---|---|
| Format: | Preprint |
| Published: |
2026
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
SCALE-Sim TPU: Validating and Extending SCALE-Sim for TPUs
by: Dang, Jingtian, et al.
Published: (2026)
by: Dang, Jingtian, et al.
Published: (2026)
Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUs
by: Zhu, Zhantong, et al.
Published: (2025)
by: Zhu, Zhantong, et al.
Published: (2025)
A Quality-Aware Voltage Overscaling Framework to Improve the Energy Efficiency and Lifetime of TPUs based on Statistical Error Modeling
by: Senobari, Alireza, et al.
Published: (2024)
by: Senobari, Alireza, et al.
Published: (2024)
FusionCIM: Accelerating LLM Inference with Fusion-Driven Computing-in-Memory Architecture
by: Xuan, Zihao, et al.
Published: (2026)
by: Xuan, Zihao, et al.
Published: (2026)
Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture
by: Baidya, Paresh, et al.
Published: (2022)
by: Baidya, Paresh, et al.
Published: (2022)
Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design
by: Pan, Tianwei, et al.
Published: (2025)
by: Pan, Tianwei, et al.
Published: (2025)
A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs
by: Dang, Peng, et al.
Published: (2024)
by: Dang, Peng, et al.
Published: (2024)
High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography
by: Tan, Weihang, et al.
Published: (2021)
by: Tan, Weihang, et al.
Published: (2021)
Field-Programmable Gate Array Architecture for Deep Learning: Survey & Future Directions
by: Boutros, Andrew, et al.
Published: (2024)
by: Boutros, Andrew, et al.
Published: (2024)
FractalCloud: A Fractal-Inspired Architecture for Efficient Large-Scale Point Cloud Processing
by: Fu, Yuzhe, et al.
Published: (2025)
by: Fu, Yuzhe, et al.
Published: (2025)
Microbenchmarking NVIDIA's Blackwell Architecture: An in-depth Architectural Analysis
by: Jarmusch, Aaron, et al.
Published: (2025)
by: Jarmusch, Aaron, et al.
Published: (2025)
Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication
by: Nojehdeh, Mohammadreza Esmali, et al.
Published: (2025)
by: Nojehdeh, Mohammadreza Esmali, et al.
Published: (2025)
High-Security Hardware Module with PUF and Hybrid Cryptography for Data Security
by: Amael, Joshua Tito, et al.
Published: (2024)
by: Amael, Joshua Tito, et al.
Published: (2024)
CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing
by: Zhang, Jingyao, et al.
Published: (2025)
by: Zhang, Jingyao, et al.
Published: (2025)
RejSCore: Rejection Sampling Core for Multivariate-based Public key Cryptography
by: Imran, Malik, et al.
Published: (2025)
by: Imran, Malik, et al.
Published: (2025)
Evaluation of isolation design flow (IDF) for Single Chip Cryptography (SCC) application
by: Malik, Arsalan Ali
Published: (2025)
by: Malik, Arsalan Ali
Published: (2025)
The Future of Memory: Limits and Opportunities
by: Dayo, Samuel, et al.
Published: (2025)
by: Dayo, Samuel, et al.
Published: (2025)
Reconfigurable Stream Network Architecture
by: Wang, Chengyue, et al.
Published: (2024)
by: Wang, Chengyue, et al.
Published: (2024)
FPPS: An FPGA-Based Point Cloud Processing System
by: Zhou, Xiaofeng, et al.
Published: (2026)
by: Zhou, Xiaofeng, et al.
Published: (2026)
Accelerating Post-Quantum Cryptography via LLM-Driven Hardware-Software Co-Design
by: Liao, Yuchao, et al.
Published: (2026)
by: Liao, Yuchao, et al.
Published: (2026)
Error Detection Schemes for Barrett Reduction of CT-BU on FPGA in Post Quantum Cryptography
by: Baidya, Paresh, et al.
Published: (2025)
by: Baidya, Paresh, et al.
Published: (2025)
Potential and Limitation of High-Frequency Cores and Caches
by: Pai, Kunal, et al.
Published: (2024)
by: Pai, Kunal, et al.
Published: (2024)
LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
by: Bhandari, Jitendra, et al.
Published: (2024)
by: Bhandari, Jitendra, et al.
Published: (2024)
In-Memory Computing Architecture for Efficient Hardware Security
by: Ajmi, Hala, et al.
Published: (2024)
by: Ajmi, Hala, et al.
Published: (2024)
Augmenting Von Neumann's Architecture for an Intelligent Future
by: Singh, Rajpreet, et al.
Published: (2025)
by: Singh, Rajpreet, et al.
Published: (2025)
Benchmarking and Dissecting the Nvidia Hopper GPU Architecture
by: Luo, Weile, et al.
Published: (2024)
by: Luo, Weile, et al.
Published: (2024)
Efficient Layered New Bit-Flipping QC-MDPC Decoder for BIKE Post-Quantum Cryptography
by: Cai, Jiaxuan, et al.
Published: (2024)
by: Cai, Jiaxuan, et al.
Published: (2024)
EMiX: Emulating Beyond Single-FPGA Limits
by: Kropotov, Alexander, et al.
Published: (2026)
by: Kropotov, Alexander, et al.
Published: (2026)
To Overlay or to Customize? Revisiting Architectural Choices in Heterogeneous Systems
by: Chen, Xingzhen, et al.
Published: (2026)
by: Chen, Xingzhen, et al.
Published: (2026)
A Data-Driven Dynamic Execution Orchestration Architecture
by: Bai, Zhenyu, et al.
Published: (2026)
by: Bai, Zhenyu, et al.
Published: (2026)
DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration
by: Chen, Xingzhen, et al.
Published: (2026)
by: Chen, Xingzhen, et al.
Published: (2026)
Optimizing GEMM for Energy and Performance on Versal ACAP Architectures
by: Papalamprou, Ilias, et al.
Published: (2025)
by: Papalamprou, Ilias, et al.
Published: (2025)
The Survey of Chiplet-based Integrated Architecture: An EDA perspective
by: Chen, Shixin, et al.
Published: (2024)
by: Chen, Shixin, et al.
Published: (2024)
Optimized Spatial Architecture Mapping Flow for Transformer Accelerators
by: Xu, Haocheng, et al.
Published: (2024)
by: Xu, Haocheng, et al.
Published: (2024)
Energy-Oriented Computing Architecture Simulator for SNN Training
by: Ma, Yunhao, et al.
Published: (2025)
by: Ma, Yunhao, et al.
Published: (2025)
A Dense and Efficient Instruction Set Architecture Encoding
by: Maroun, Emad Jacob
Published: (2025)
by: Maroun, Emad Jacob
Published: (2025)
Switchable Single/Dual Edge Registers for Pipeline Architecture
by: Singh, Suyash Vardhan, et al.
Published: (2024)
by: Singh, Suyash Vardhan, et al.
Published: (2024)
An Architectural Error Metric for CNN-Oriented Approximate Multipliers
by: Liu, Ao, et al.
Published: (2024)
by: Liu, Ao, et al.
Published: (2024)
Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models
by: Peng, Huwan, et al.
Published: (2023)
by: Peng, Huwan, et al.
Published: (2023)
YOCO: A Hybrid In-Memory Computing Architecture with 8-bit Sub-PetaOps/W In-Situ Multiply Arithmetic for Large-Scale AI
by: Xuan, Zihao, et al.
Published: (2023)
by: Xuan, Zihao, et al.
Published: (2023)
Similar Items
-
SCALE-Sim TPU: Validating and Extending SCALE-Sim for TPUs
by: Dang, Jingtian, et al.
Published: (2026) -
Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUs
by: Zhu, Zhantong, et al.
Published: (2025) -
A Quality-Aware Voltage Overscaling Framework to Improve the Energy Efficiency and Lifetime of TPUs based on Statistical Error Modeling
by: Senobari, Alireza, et al.
Published: (2024) -
FusionCIM: Accelerating LLM Inference with Fusion-Driven Computing-in-Memory Architecture
by: Xuan, Zihao, et al.
Published: (2026) -
Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture
by: Baidya, Paresh, et al.
Published: (2022)