Code size reduction by advanced near addressing modes
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arXiv
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| Hauptverfasser: | , , , , |
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| Format: | Preprint |
| Veröffentlicht: |
2026
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| _version_ | 1866910270641668096 |
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| author | Nuernberger, Kajetan Roecker, Thomas Fueto, Gergely Spaits, Gabor Lehser, Horst |
| author_facet | Nuernberger, Kajetan Roecker, Thomas Fueto, Gergely Spaits, Gabor Lehser, Horst |
| contents | To enable debugging and calibration of real time systems, which are in interaction with the real plant, the software used on those systems often has a huge number of global variables. The huge number of global variables exceed the range addressable relative to the global pointer. Therefore, addressing these variables normally needs two instructions. Other CPU architectures commonly used in the real time control systems domain address these by various near addressing modes. This results in significant code size reductions and performance boost. This paper discusses different variants to add such near addressing features to the RISC-V ISA. The impact on the code size is evaluated with different representative workloads. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_25602 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Code size reduction by advanced near addressing modes Nuernberger, Kajetan Roecker, Thomas Fueto, Gergely Spaits, Gabor Lehser, Horst Hardware Architecture To enable debugging and calibration of real time systems, which are in interaction with the real plant, the software used on those systems often has a huge number of global variables. The huge number of global variables exceed the range addressable relative to the global pointer. Therefore, addressing these variables normally needs two instructions. Other CPU architectures commonly used in the real time control systems domain address these by various near addressing modes. This results in significant code size reductions and performance boost. This paper discusses different variants to add such near addressing features to the RISC-V ISA. The impact on the code size is evaluated with different representative workloads. |
| title | Code size reduction by advanced near addressing modes |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2605.25602 |