When NPUs Are Not Always Faster: A Stage-Level Analysis of Mobile LLM Inference
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| Format: | Preprint |
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2026
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| _version_ | 1866918524976365568 |
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| author | Li, Pu Qi, Jiawen Chen, Qinyu |
| author_facet | Li, Pu Qi, Jiawen Chen, Qinyu |
| contents | Deploying large language models (LLMs) on mobile devices increasingly relies on heterogeneous execution, yet no prior study has systematically characterized NPU effectiveness at the operator and pipeline level. We present the first stage-aware, multi-level benchmarking study of mobile LLM inference on a CPU-NPU heterogeneous SoC. We introduce an OPMASK-based controlled pipeline decomposition methodology that isolates communication, quantization, and computation overheads within the NPU execution path. Our results reveal a counter-intuitive stage-level performance reversal: CPUs outperform NPUs in the compute-intensive Prefill stage (up to 1.6x), while NPUs provide only limited acceleration in the memory-bound Decode stage (1.05-1.2x). We further show that scheduling overhead and cross-backend fallback reduce the practical benefits of NPU offloading. For the energy trend, increasing NPU offloading leads to higher energy consumption (up to 51%). Based on these findings, we derive design guidelines for NPU architects targeting on-device LLM inference. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2605_27435 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | When NPUs Are Not Always Faster: A Stage-Level Analysis of Mobile LLM Inference Li, Pu Qi, Jiawen Chen, Qinyu Hardware Architecture Artificial Intelligence Deploying large language models (LLMs) on mobile devices increasingly relies on heterogeneous execution, yet no prior study has systematically characterized NPU effectiveness at the operator and pipeline level. We present the first stage-aware, multi-level benchmarking study of mobile LLM inference on a CPU-NPU heterogeneous SoC. We introduce an OPMASK-based controlled pipeline decomposition methodology that isolates communication, quantization, and computation overheads within the NPU execution path. Our results reveal a counter-intuitive stage-level performance reversal: CPUs outperform NPUs in the compute-intensive Prefill stage (up to 1.6x), while NPUs provide only limited acceleration in the memory-bound Decode stage (1.05-1.2x). We further show that scheduling overhead and cross-backend fallback reduce the practical benefits of NPU offloading. For the energy trend, increasing NPU offloading leads to higher energy consumption (up to 51%). Based on these findings, we derive design guidelines for NPU architects targeting on-device LLM inference. |
| title | When NPUs Are Not Always Faster: A Stage-Level Analysis of Mobile LLM Inference |
| topic | Hardware Architecture Artificial Intelligence |
| url | https://arxiv.org/abs/2605.27435 |