elasticAI.explorer: Towards a Unified End-to-End Framework for Hardware-Aware Neural Architecture Search

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Maman, Natalie, Hettstedt, Florian, Erbslöh, Andreas, Schiele, Gregor
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Towards an End-To-End System for Real-Time Gesture Recognition from Surface Vibrations
by: Hettstedt, Florian, et al.
Published: (2026)

Precomputed 1D-CNNs for Atrial Fibrillation Detection on Tiny Smart Sensor Systems
by: Einhaus, Lukas, et al.
Published: (2026)

MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI
by: M, Ajay Kumar, et al.
Published: (2025)

Energy Efficient LSTM Accelerators for Embedded FPGAs through Parameterised Architecture Design
by: Qian, Chao, et al.
Published: (2026)

AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance
by: Kang, Seungkwan, et al.
Published: (2026)

MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules
by: Raj, Ritik, et al.
Published: (2025)

HSCO-Bench: An Agent-Driven End-to-End Hardware-Software Co-design Benchmark for Systems-on-Chip
by: Tsai, Pei-Huan, et al.
Published: (2026)

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification
by: Wan, Gwok-Waa, et al.
Published: (2025)

MiCo: End-to-End Mixed Precision Neural Network Co-Exploration Framework for Edge AI
by: Jiang, Zijun, et al.
Published: (2025)

T-MAN: Enabling End-to-End Low-Bit LLM Inference on NPUs via Unified Table Lookup
by: Wei, Jianyu, et al.
Published: (2025)

Cool-3D: An End-to-End Thermal-Aware Framework for Early-Phase Design Space Exploration of Microfluidic-Cooled 3DICs
by: Wang, Runxi, et al.
Published: (2025)

Voyager: An End-to-End Framework for Design-Space Exploration and Generation of DNN Accelerators
by: Prabhu, Kartik, et al.
Published: (2025)

MemIntelli: A Generic End-to-End Simulation Framework for Memristive Intelligent Computing
by: Zhou, Houji, et al.
Published: (2025)

Who Checks the Checker? Enhancing Component-level Architectural SEU Fault Tolerance for End-to-End SoC Protection
by: Rogenmoser, Michael, et al.
Published: (2026)

End-to-End Transformer Acceleration Through Processing-in-Memory Architectures
by: Yang, Xiaoxuan, et al.
Published: (2025)

CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device
by: and, Yan-Cheng Guo, et al.
Published: (2025)

NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI
by: Yang, Hanchen, et al.
Published: (2025)

PowerFlow-DNN: Compiler-Directed Fine-Grained Power Orchestration for End-to-End Edge AI Inference
by: Chen, Paul, et al.
Published: (2026)

Efficient yet Accurate End-to-End SC Accelerator Design
by: Li, Meng, et al.
Published: (2024)

PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators
by: Sun, Xiaotian, et al.
Published: (2024)

Idle is the New Sleep: Configuration-Aware Alternative to Powering Off FPGA-Based DL Accelerators During Inactivity
by: Qian, Chao, et al.
Published: (2024)

Mamba-X: An End-to-End Vision Mamba Accelerator for Edge Computing Devices
by: Yoon, Dongho, et al.
Published: (2025)

Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms
by: Wang, Zhihai, et al.
Published: (2024)

Hardware-Aware Neural Dropout Search for Reliable Uncertainty Prediction on FPGA
by: Zhang, Zehuan, et al.
Published: (2024)

SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design
by: Alvanaki, Elisavet Lydia, et al.
Published: (2025)

FASE: FPGA-Assisted Syscall Emulation for Rapid End-to-End Processor Performance Validation
by: Meng, Chengzhen, et al.
Published: (2025)

Towards the Certification of Hybrid Architectures: Analysing Interference on Hardware Accelerators through PML
by: Lesage, Benjamin, et al.
Published: (2024)

HyperCroc: End-to-End Open-Source RISC-V MCU with a Plug-In Interface for Domain-Specific Accelerators
by: Sauter, Philippe, et al.
Published: (2026)

System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints
by: Liao, Yuchao, et al.
Published: (2024)

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques
by: Canpolat, Oğuzhan, et al.
Published: (2025)

GenPairX: A Hardware-Algorithm Co-Designed Accelerator for Paired-End Read Mapping
by: Eudine, Julien, et al.
Published: (2026)

Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture
by: Wan, Zishen, et al.
Published: (2024)

Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS
by: Scheffler, Paul, et al.
Published: (2024)

ElasticAI: Creating and Deploying Energy-Efficient Deep Learning Accelerator for Pervasive Computing
by: Qian, Chao, et al.
Published: (2024)

Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning
by: Kanda, R., et al.
Published: (2026)

TriGen: NPU Architecture for End-to-End Acceleration of Large Language Models based on SW-HW Co-Design
by: Lee, Jonghun, et al.
Published: (2026)

Torch2Chip: An End-to-end Customizable Deep Neural Network Compression and Deployment Toolkit for Prototype Hardware Accelerator Design
by: Meng, Jian, et al.
Published: (2024)

A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models
by: Sharma, Harsh, et al.
Published: (2023)

In-Memory Computing Architecture for Efficient Hardware Security
by: Ajmi, Hala, et al.
Published: (2024)

PD-Swap: Prefill-Decode Logic Swapping for End-to-End LLM Inference on Edge FPGAs via Dynamic Partial Reconfiguration
by: Zhang, Yifan, et al.
Published: (2025)