Imagen de Portada

FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor with Tomasulo-Style Dynamic Scheduling

Fuente: arXiv

Guardado en:

Detalles Bibliográficos
Autores principales:	Giorgi, Roberto, Planas, Miquel Moretó
Formato:	Preprint
Publicado:	2026
Materias:	Hardware Architecture Performance C.1.1; I.6.0; C.4
Acceso en línea:	Acceder al recurso
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

Ejemplares similares

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm
por: Giorgi, Roberto
Publicado: (2025)

An Integrated UVM-TLM Co-Simulation Framework for RISC-V Functional Verification and Performance Evaluation
por: Qiu, Ruizhi, et al.
Publicado: (2025)

HERMES: High-Performance RISC-V Memory Hierarchy for ML Workloads
por: Suryadevara, Pranav
Publicado: (2025)

Web-Based Simulator of Superscalar RISC-V Processors
por: Jaros, Jiri, et al.
Publicado: (2024)

basic_RV32s: An Open-Source Microarchitectural Roadmap for RISC-V RV32I
por: Kang, Hyun Woo, et al.
Publicado: (2025)

RV-IM100: Quantifying ISA Extension, Datapath Width, and Pipeline Depth Trade-offs in RISC-V Microarchitectures
por: Kang, Hyunwoo
Publicado: (2026)

A Comparative Analysis of ARM and x86-64 Laptop-Class Processors: Architecture, Assembly-Level Performance, and Energy Efficiency
por: Özyılmaz, Mustafa Mert
Publicado: (2026)

Glass-Box Analysis for Computer Systems: Transparency Index, Shapley Attribution, and Markov Models of Branch Prediction
por: Alpay, Faruk, et al.
Publicado: (2025)

Taming Wild Branches: Overcoming Hard-to-Predict Branches using the Bullseye Predictor
por: Behrendt, Emet, et al.
Publicado: (2025)

Design Space Exploration of Approximate Computing Techniques with a Reinforcement Learning Approach
por: Saeedi, Sepide, et al.
Publicado: (2023)

How long can you sleep? Idle Time System Inefficiencies and Opportunities
por: Antoniou, Georgia, et al.
Publicado: (2025)

Multi-diseases detection with memristive system on chip
por: Wang, Zihan, et al.
Publicado: (2024)

Fast NF4 Dequantization Kernels for Large Language Model Inference
por: Qi, Xiangbo, et al.
Publicado: (2026)

Application-Driven Exascale: The JUPITER Benchmark Suite
por: Herten, Andreas, et al.
Publicado: (2024)

RayFlex: An Open-Source RTL Implementation of the Hardware Ray Tracer Datapath
por: Shen, Fangjia, et al.
Publicado: (2024)

D-com: Accelerating Iterative Processing to Enable Low-rank Decomposition of Activations
por: Tahmasebi, Faraz, et al.
Publicado: (2025)

CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST
por: Goswami, Kaustav, et al.
Publicado: (2026)

parti-gem5: gem5's Timing Mode Parallelised
por: Cubero-Cascante, José, et al.
Publicado: (2023)

Rotary GPU: Exploring Local Execution Paths for Large Mixture-of-Experts Models Under Limited GPU Memory
por: Jo, Myeong Jun
Publicado: (2026)

FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices
por: Parameshwara, Arya, et al.
Publicado: (2025)

Floating Point HUB Adder for RISC-V Sargantana Processor
por: Bandera, Gerardo, et al.
Publicado: (2024)

RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI
por: Yildirim, Muhammed, et al.
Publicado: (2025)

Functional ISS-Driven Verification of Superscalar RISC-V Processors
por: Galimberti, Andrea, et al.
Publicado: (2024)

SynapticCore-X: A Modular Neural Processing Architecture for Low-Cost FPGA Acceleration
por: Parameshwara, Arya
Publicado: (2025)

A Flexible Instruction Set Architecture for Efficient GEMMs
por: Santana, Alexandre de Limas, et al.
Publicado: (2025)

Tekum: Balanced Ternary Tapered Precision Real Arithmetic
por: Hunhold, Laslo
Publicado: (2025)

WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes
por: Giorgi, Roberto, et al.
Publicado: (2025)

Splitwise: Efficient generative LLM inference using phase splitting
por: Patel, Pratyush, et al.
Publicado: (2023)

FlexiBit: Fully Flexible Precision Bit-parallel Accelerator Architecture for Arbitrary Mixed Precision AI
por: Tahmasebi, Faraz, et al.
Publicado: (2024)

SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts
por: Prabhakar, Raghu, et al.
Publicado: (2024)

Mestra: Exploring Migration on Virtualized CGRAs
por: Kyriazis, Agamemnon, et al.
Publicado: (2026)

Design and implementation of a synchronous Hardware Performance Monitor for a RISC-V space-oriented processor
por: Arribas, Miguel Jiménez, et al.
Publicado: (2024)

A Per-Access Upper Bound for Shared-Resource Interference in Direct-Mapped Multicore Architectures
por: Pedroni, Felipe T.
Publicado: (2026)

Aurora: Architecting Argonne's First Exascale Supercomputer for Accelerated Scientific Discovery
por: Allcock, William E., et al.
Publicado: (2025)

GDEV-AI: A Generalized Evaluation of Deep Learning Inference Scaling and Architectural Saturation
por: Palaniappan, Kathiravan
Publicado: (2026)

OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
por: Lebold, Denis, et al.
Publicado: (2026)

Streamlining SIMD ISA Extensions with Takum Arithmetic: A Case Study on Intel AVX10.2
por: Hunhold, Laslo
Publicado: (2025)

Chameleon: Adaptive Caching and Scheduling for Many-Adapter LLM Inference Environments
por: Iliakopoulou, Nikoleta, et al.
Publicado: (2024)

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing
por: Yadav, Priyanshu
Publicado: (2025)

Evaluating the Impact of Packet Scheduling and Congestion Control Algorithms on MPTCP Performance over Heterogeneous Networks
por: Dimopoulos, Dimitrios, et al.
Publicado: (2025)