A Reconfigurable Computing In-Memory Macro with Charge-sharing-based Weighted Accumulator
Fuente:
arXiv
Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2026
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866914615751868416 |
|---|---|
| author | Yang, Junyi Dong, Shuai Fu, Zhengnan Shang, Hongyang Basu, Arindam |
| author_facet | Yang, Junyi Dong, Shuai Fu, Zhengnan Shang, Hongyang Basu, Arindam |
| contents | SRAM-based analog computing-in-memory demonstrates outstanding efficiency. However, it faces three critical challenges: significant ADC overhead, high latency for multi-bit inputs, and limited read bitline voltage. To address these issues, this work proposes a multi-bit highly reconfigurable 256x128 in-memory computing array supporting 1-7b input, 2-4b weight, and 1-7b output. Three key innovations are introduced: 1) The IMADC occupies only 3% area overhead, achieving a 9x improvement compared to previous IMADC; 2) The BSCHA reduces latency by 1.9x and 6.6x compared to traditional pulse-width modulation (PWM) and bit-slicing modes, respectively; 3) A dual-8T bitcell enabling ternary weight storage through a decoupled read path, integrated with a read wordline under-driven cascode technique, improves linearity of unit discharge current by 7x and increases the usable read bitline voltage by 3.5x. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_30814 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | A Reconfigurable Computing In-Memory Macro with Charge-sharing-based Weighted Accumulator Yang, Junyi Dong, Shuai Fu, Zhengnan Shang, Hongyang Basu, Arindam Hardware Architecture SRAM-based analog computing-in-memory demonstrates outstanding efficiency. However, it faces three critical challenges: significant ADC overhead, high latency for multi-bit inputs, and limited read bitline voltage. To address these issues, this work proposes a multi-bit highly reconfigurable 256x128 in-memory computing array supporting 1-7b input, 2-4b weight, and 1-7b output. Three key innovations are introduced: 1) The IMADC occupies only 3% area overhead, achieving a 9x improvement compared to previous IMADC; 2) The BSCHA reduces latency by 1.9x and 6.6x compared to traditional pulse-width modulation (PWM) and bit-slicing modes, respectively; 3) A dual-8T bitcell enabling ternary weight storage through a decoupled read path, integrated with a read wordline under-driven cascode technique, improves linearity of unit discharge current by 7x and increases the usable read bitline voltage by 3.5x. |
| title | A Reconfigurable Computing In-Memory Macro with Charge-sharing-based Weighted Accumulator |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2605.30814 |