Cover Image

Formal Verification of Secure Encrypted Virtualization

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Weerasena, Hansika, Das, Amitabh, Mishra, Prabhat
Format:	Preprint
Published:	2026
Subjects:	Cryptography and Security Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Breaking On-Chip Communication Anonymity using Flow Correlation Attacks
by: Weerasena, Hansika, et al.
Published: (2023)

Revealing CNN Architectures via Side-Channel Analysis in Dataflow-based Inference Accelerators
by: Weerasena, Hansika, et al.
Published: (2023)

Secure Multi-Path Routing with All-or-Nothing Transform for Network-on-Chip Architectures
by: Weerasena, Hansika, et al.
Published: (2026)

TroLL: Exploiting Structural Similarities between Logic Locking and Hardware Trojans
by: Liu, Yuntao, et al.
Published: (2023)

Modern Hardware Security: A Review of Attacks and Countermeasures
by: Mishra, Jyotiprakash, et al.
Published: (2025)

NTTSuite: Number Theoretic Transform Benchmarks for Accelerating Encrypted Computation
by: Ding, Juran, et al.
Published: (2024)

PA-Boot: A Formally Verified Authentication Protocol for Multiprocessor Secure Boot
by: Zhang, Zhuoruo, et al.
Published: (2022)

Design for Trust utilizing Rareness Reduction
by: Jayasena, Aruna, et al.
Published: (2023)

GPU Acceleration of TFHE-Based High-Precision Nonlinear Layers for Encrypted LLM Inference
by: Chen, Guoci, et al.
Published: (2026)

RTL2M$μ$PATH: Multi-$μ$PATH Synthesis with Applications to Hardware Security Verification
by: Hsiao, Yao, et al.
Published: (2024)

NuRedact: Non-Uniform eFPGA Architecture for Low-Overhead and Secure IP Redaction
by: Das, Voktho, et al.
Published: (2026)

Bridging the Gap between Hardware Fuzzing and Industrial Verification
by: Ma, Ruiyang, et al.
Published: (2025)

Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
by: Raj, Kshitij, et al.
Published: (2025)

High-Security Hardware Module with PUF and Hybrid Cryptography for Data Security
by: Amael, Joshua Tito, et al.
Published: (2024)

Secure Scattered Memory: Rethinking Secure Enclave Memory with Secret Sharing
by: Geng, Haoran, et al.
Published: (2024)

aLEAKator: HDL Mixed-Domain Simulation for Masked Hardware \& Software Formal Verification
by: Amiot, Noé, et al.
Published: (2025)

ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification
by: Monfared, Saleh Khalaj, et al.
Published: (2025)

Topology-aware Detection and Localization of Distributed Denial-of-Service Attacks in Network-on-Chips
by: Weerasena, Hansika, et al.
Published: (2025)

Supporting Secured Integration of Microarchitectural Defenses
by: Ramkrishnan, Kartik, et al.
Published: (2026)

Security Properties for Open-Source Hardware Designs
by: Rogers, Jayden, et al.
Published: (2024)

On the Importance of Reproducibility of Experimental Results Especially in the Domain of Security
by: Petryk, Dmytro, et al.
Published: (2024)

Efficient and Lightweight In-memory Computing Architecture for Hardware Security
by: Ajmi, Hala, et al.
Published: (2022)

New Security Challenges Towards In-Sensor Computing Systems
by: Kajol, Mashrafi, et al.
Published: (2025)

REDACTOR: eFPGA Redaction for DNN Accelerator Security
by: Baddour, Yazan, et al.
Published: (2025)

GPU in the Blind Spot: Overlooked Security Risks in Transportation
by: Puspa, Sefatun-Noor, et al.
Published: (2025)

The Avatar Cache: Enabling On-Demand Security with Morphable Cache Architecture
by: Bhatla, Anubhav, et al.
Published: (2026)

MINT: Securely Mitigating Rowhammer with a Minimalist In-DRAM Tracker
by: Qureshi, Moinuddin, et al.
Published: (2024)

CIBPU: A Conflict-Invisible Secure Branch Prediction Unit
by: Zhou, Zhe, et al.
Published: (2025)

Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip
by: Mulhem, Saleh, et al.
Published: (2024)

Fastrack: Fast IO for Secure ML using GPU TEEs
by: Wang, Yongqin, et al.
Published: (2024)

PoSyn: Secure Power Side-Channel Aware Synthesis
by: Srivastava, Amisha, et al.
Published: (2025)

FAME: FPGA Acceleration of Secure Matrix Multiplication with Homomorphic Encryption
by: Xu, Zhihan, et al.
Published: (2025)

MOAT: Securely Mitigating Rowhammer with Per-Row Activation Counters
by: Qureshi, Moinuddin, et al.
Published: (2024)

AMuLeT: Automated Design-Time Testing of Secure Speculation Countermeasures
by: Fu, Bo, et al.
Published: (2025)

RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective
by: Pinto, Sandro, et al.
Published: (2024)

ShadowBinding: Realizing Effective Microarchitectures for In-Core Secure Speculation Schemes
by: Kvalsvik, Amund Bergland, et al.
Published: (2025)

SecScale: A Scalable and Secure Trusted Execution Environment for Servers
by: Sunny, Ani, et al.
Published: (2024)

Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance
by: Canpolat, Oğuzhan, et al.
Published: (2025)

"vcd2df" -- Leveraging Data Science Insights for Hardware Security Research
by: Deutschbein, Calvin, et al.
Published: (2025)

Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance
by: Canpolat, Oğuzhan, et al.
Published: (2024)