A 32-Channel 3.53-μW Per Channel Brain-Machine Interface SoC Featuring Dual-Threshold Delta-modulation, In-Memory Spike Detection and Bi-SNN Based Motor Decoding
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arXiv
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| Autores principales: | , , , , , , , , , , |
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| Formato: | Preprint |
| Publicado: |
2026
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| Materias: | |
| Acceso en línea: | |
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| _version_ | 1866917553596530688 |
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| author | Ke, Ye Fu, Zhengnan Sun, Pao-Sheng Vincent Guo, An Dong, Shuai Yang, Junyi Yang, Yahan Eldaly, Abdelrahman B. M. Si, Xin Chan, Leanne Basu, Arindam |
| author_facet | Ke, Ye Fu, Zhengnan Sun, Pao-Sheng Vincent Guo, An Dong, Shuai Yang, Junyi Yang, Yahan Eldaly, Abdelrahman B. M. Si, Xin Chan, Leanne Basu, Arindam |
| contents | With the scaling of sensor channel counts, systems confront challenges in frontend data sensing and on-implant data processing. This work presents a 32-channel fully event-based iBMI SoC in 65nm CMOS for an efficient neuromorphic signal processing pipeline. The SoC integrates a 32-channel dual-threshold delta modulation (DTDM) frontend array that provides up to 26x data compression at the frontend, an in-memory computing (IMC) spike detector (SPD) for efficient in-pixel spike detection, and a bipolar LIF-based spiking neural network (Bi-SNN) decoder for on-chip motor intention decoding (MID). Consuming only 3.53 μW per channel and achieving ~0.62 decoding R2 with a compact 0.034 mm2 per-channel area, the chip enables high-efficiency signal recording, processing, and decoding for implantable devices. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2606_01776 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | A 32-Channel 3.53-μW Per Channel Brain-Machine Interface SoC Featuring Dual-Threshold Delta-modulation, In-Memory Spike Detection and Bi-SNN Based Motor Decoding Ke, Ye Fu, Zhengnan Sun, Pao-Sheng Vincent Guo, An Dong, Shuai Yang, Junyi Yang, Yahan Eldaly, Abdelrahman B. M. Si, Xin Chan, Leanne Basu, Arindam Signal Processing With the scaling of sensor channel counts, systems confront challenges in frontend data sensing and on-implant data processing. This work presents a 32-channel fully event-based iBMI SoC in 65nm CMOS for an efficient neuromorphic signal processing pipeline. The SoC integrates a 32-channel dual-threshold delta modulation (DTDM) frontend array that provides up to 26x data compression at the frontend, an in-memory computing (IMC) spike detector (SPD) for efficient in-pixel spike detection, and a bipolar LIF-based spiking neural network (Bi-SNN) decoder for on-chip motor intention decoding (MID). Consuming only 3.53 μW per channel and achieving ~0.62 decoding R2 with a compact 0.034 mm2 per-channel area, the chip enables high-efficiency signal recording, processing, and decoding for implantable devices. |
| title | A 32-Channel 3.53-μW Per Channel Brain-Machine Interface SoC Featuring Dual-Threshold Delta-modulation, In-Memory Spike Detection and Bi-SNN Based Motor Decoding |
| topic | Signal Processing |
| url | https://arxiv.org/abs/2606.01776 |