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CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees

Fuente: arXiv

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Bibliographic Details
Main Authors:	Leone, Lorenzo, Wiese, Philip, İslamoğlu, Gamze, Rogenmoser, Michael, Rossi, Davide, Conti, Francesco, Benini, Luca
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
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