A methodological approach for asynchronous implementation of the Rijndael Algorithm
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| Format: | Artículo científico |
| Langue: | en |
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Universidad del Valle
2013
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| _version_ | 1876442448096395264 |
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| author | Rubén D. Nieto |
| author_facet | Rubén D. Nieto |
| contents | A methodological approach for asynchronous implementation of the Rijndael Algorithm Rubén D. Nieto Álvaro Bernal Ingeniería FPGA Balsa Rijndael Asynchronous This article describes the implementation methodology of Rijndael algorithm to encryption process, by using asynchronous design with assistance of the software tool Balsa, for functional simulation, description and synthesis of asynchronous digital circuits. The main results presented correspond to implementations that use the codification protocols dual-rail and 1-of-4, for blocks of data and keys of 128 bits over a field-programmable gate array (FPGA) hardware platform. The Xilinx ISE tool was used showing a full integration level with the Balsa system. 2013 artículo científico 0123-3033 https://www.redalyc.org/articulo.oa?id=291329166008 en http://www.redalyc.org/revista.oa?id=2913 Ingeniería y Competitividad application/pdf Universidad del Valle Ingeniería y Competitividad (Colombia) Num.2 Vol.15 |
| format | Artículo científico |
| id | redalyc_291329166008 |
| institution | Redalyc |
| language | en |
| publishDate | 2013 |
| publisher | Universidad del Valle |
| spellingShingle | A methodological approach for asynchronous implementation of the Rijndael Algorithm Rubén D. Nieto Ingeniería FPGA Balsa Rijndael Asynchronous A methodological approach for asynchronous implementation of the Rijndael Algorithm Rubén D. Nieto Álvaro Bernal Ingeniería FPGA Balsa Rijndael Asynchronous This article describes the implementation methodology of Rijndael algorithm to encryption process, by using asynchronous design with assistance of the software tool Balsa, for functional simulation, description and synthesis of asynchronous digital circuits. The main results presented correspond to implementations that use the codification protocols dual-rail and 1-of-4, for blocks of data and keys of 128 bits over a field-programmable gate array (FPGA) hardware platform. The Xilinx ISE tool was used showing a full integration level with the Balsa system. 2013 artículo científico 0123-3033 https://www.redalyc.org/articulo.oa?id=291329166008 en http://www.redalyc.org/revista.oa?id=2913 Ingeniería y Competitividad application/pdf Universidad del Valle Ingeniería y Competitividad (Colombia) Num.2 Vol.15 |
| title | A methodological approach for asynchronous implementation of the Rijndael Algorithm |
| topic | Ingeniería FPGA Balsa Rijndael Asynchronous |
| url | https://www.redalyc.org/articulo.oa?id=291329166008 |