Verification of transaction level models of embedded systems
Fuente:
Redalyc
Salvato in:
| Autore principale: | |
|---|---|
| Natura: | Artículo científico |
| Lingua: | en |
| Pubblicazione: |
Universidad de Costa Rica
2013
|
| Soggetti: | |
| Accesso online: | |
| Tags: |
Aggiungi Tag
Nessun Tag, puoi essere il primo ad aggiungerne!!
|
| _version_ | 1876448122891141120 |
|---|---|
| author | Lucky Lochi Yu Lo |
| author_facet | Lucky Lochi Yu Lo |
| contents | Verification of transaction level models of embedded systems Lucky Lochi Yu Lo Ingeniería Embedded systems formal verification transaction level models As complexity increases in embedded systems design, there is need for more time for verification purposes. For embedded systems, the only verification that can be done is running test cases, and the number of cases increases exponentially. In order to shorten this verification phase of the design, we propose a methodology to do formal verification of embedded systems. In formal verification no test cases are needed, but an mathematical analysis of the original model and the refined one. At the present, there is no proven formal verification techniques for a system level design of an embedded system. In this article, we present a brief summary of Model Algebra, present two new transformation rules and experimental results in isomorphism checking based on these rules. We test this transformation rules in various scenarios and prove that it is a promising methodology to improve embedded system design. 2013 artículo científico 1409-2441 https://www.redalyc.org/articulo.oa?id=44170529005 en http://www.redalyc.org/revista.oa?id=441 Ingeniería. Revista de la Universidad de Costa Rica application/pdf Universidad de Costa Rica Ingeniería. Revista de la Universidad de Costa Rica (Costa Rica) Num.2 Vol.23 |
| format | Artículo científico |
| id | redalyc_44170529005 |
| institution | Redalyc |
| language | en |
| publishDate | 2013 |
| publisher | Universidad de Costa Rica |
| spellingShingle | Verification of transaction level models of embedded systems Lucky Lochi Yu Lo Ingeniería Embedded systems formal verification transaction level models Verification of transaction level models of embedded systems Lucky Lochi Yu Lo Ingeniería Embedded systems formal verification transaction level models As complexity increases in embedded systems design, there is need for more time for verification purposes. For embedded systems, the only verification that can be done is running test cases, and the number of cases increases exponentially. In order to shorten this verification phase of the design, we propose a methodology to do formal verification of embedded systems. In formal verification no test cases are needed, but an mathematical analysis of the original model and the refined one. At the present, there is no proven formal verification techniques for a system level design of an embedded system. In this article, we present a brief summary of Model Algebra, present two new transformation rules and experimental results in isomorphism checking based on these rules. We test this transformation rules in various scenarios and prove that it is a promising methodology to improve embedded system design. 2013 artículo científico 1409-2441 https://www.redalyc.org/articulo.oa?id=44170529005 en http://www.redalyc.org/revista.oa?id=441 Ingeniería. Revista de la Universidad de Costa Rica application/pdf Universidad de Costa Rica Ingeniería. Revista de la Universidad de Costa Rica (Costa Rica) Num.2 Vol.23 |
| title | Verification of transaction level models of embedded systems |
| topic | Ingeniería Embedded systems formal verification transaction level models |
| url | https://www.redalyc.org/articulo.oa?id=44170529005 |