Novel design of array multiplier
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| Natura: | Artículo científico |
| Lingua: | en |
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Universidade Federal de Santa Maria
2015
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| _version_ | 1876460852895285248 |
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| author | Seyyed Masoud Razavi |
| author_facet | Seyyed Masoud Razavi |
| contents | Novel design of array multiplier Seyyed Masoud Razavi Seyyed Reza Talebiyan Estudios Ambientales power delay Array multiplier return technique return leapfrog array multiplier In this paper a new array multiplier has been proposed, which has lower power consumption than the regular array multipliers. This technique has been applied on two conventional and leapfrog array multipliers. In the formation of 8×8 mult iplier all designs proposed in this paper have been implemented using the HSPICE by the use of 180 nm TSMC technology at a supply voltage 1v. To verify the perfo rmance of the proposed structures, structures have been simulated in 130 nm & 65 nm PTM technol ogies. The simulation results show that applying the return technique in the array structures causes power consumption reduction and consequently PDP reduction. This improvem ent for 180 nm technology in the conventional array structure is 13.32 % and in th e leapfrog array structure is 23.27 %. It should be noted that this technique substantially makes the number of transistors less and as a result area reduction 2015 artículo científico 0100-8307 https://www.redalyc.org/articulo.oa?id=467547683040 en http://www.redalyc.org/revista.oa?id=4675 Ciência e Natura application/pdf Universidade Federal de Santa Maria Ciência e Natura (Brasil) Num.6-2 Vol.37 |
| format | Artículo científico |
| id | redalyc_467547683040 |
| institution | Redalyc |
| language | en |
| publishDate | 2015 |
| publisher | Universidade Federal de Santa Maria |
| spellingShingle | Novel design of array multiplier Seyyed Masoud Razavi Estudios Ambientales power delay Array multiplier return technique return leapfrog array multiplier Novel design of array multiplier Seyyed Masoud Razavi Seyyed Reza Talebiyan Estudios Ambientales power delay Array multiplier return technique return leapfrog array multiplier In this paper a new array multiplier has been proposed, which has lower power consumption than the regular array multipliers. This technique has been applied on two conventional and leapfrog array multipliers. In the formation of 8×8 mult iplier all designs proposed in this paper have been implemented using the HSPICE by the use of 180 nm TSMC technology at a supply voltage 1v. To verify the perfo rmance of the proposed structures, structures have been simulated in 130 nm & 65 nm PTM technol ogies. The simulation results show that applying the return technique in the array structures causes power consumption reduction and consequently PDP reduction. This improvem ent for 180 nm technology in the conventional array structure is 13.32 % and in th e leapfrog array structure is 23.27 %. It should be noted that this technique substantially makes the number of transistors less and as a result area reduction 2015 artículo científico 0100-8307 https://www.redalyc.org/articulo.oa?id=467547683040 en http://www.redalyc.org/revista.oa?id=4675 Ciência e Natura application/pdf Universidade Federal de Santa Maria Ciência e Natura (Brasil) Num.6-2 Vol.37 |
| title | Novel design of array multiplier |
| topic | Estudios Ambientales power delay Array multiplier return technique return leapfrog array multiplier |
| url | https://www.redalyc.org/articulo.oa?id=467547683040 |