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| Format: | Artículo científico |
| Langue: | es |
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Universidad Nacional Autónoma de México
2013
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| Accès en ligne: | https://www.redalyc.org/articulo.oa?id=47426212010 |
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| _version_ | 1866585304913149952 |
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| author | C. Villa-Angulo |
| author_facet | C. Villa-Angulo |
| contents | Implementation of a 10.24 GS/s 12-bit Optoelectronics Analog-to- Digital Converter Based on a Polyphase Demultiplexing Architecture C. Villa-Angulo I. O. Hernandez-Fuentes R. Villa-Angulo S. E. Ahumada-Valdez R. A. Ramos-Irigoyen E. Donkor Ingeniería to poly self synchronized sampling Optoelectronics analog In this paper we present the practical implementation of a high-speed polyphase sampling and demultiplexing architecture for optoelectronics analog-to-digital converters (OADCs). The architecture consists of a one-stage divideby- eight decimator circuit where optically-triggered samplers are cascaded to sample an analog input signal, and demultiplex different phases of the sampled signal to yield low data rate for electronic quantization. Electrical-in to electrical-out data format is maintained through the sampling, demultiplexing and quantization processes of the architecture thereby avoiding the need for electrical-to-optical and optical-to-electrical signal conversions. We experimentally demonstrate a 10.24 giga samples per second (GS/s), 12-bit resolution OADC system comprising the optically-triggered sampling circuits integrated with commercial electronic quantizers. Measurements performed on the OADC yielded an effective bit resolution (ENOB) of 10.3 bits, spurious free dynamic range (SFDR) of -32 dB and signal-to-noise and distortion ratio (SNDR) of 63.7 dB. 2013 artículo científico 1665-6423 https://www.redalyc.org/articulo.oa?id=47426212010 es http://www.redalyc.org/revista.oa?id=474 Journal of Applied Research and Technology application/pdf Universidad Nacional Autónoma de México Journal of Applied Research and Technology (México) Num.1 Vol.11 |
| format | Artículo científico |
| id | redalyc_47426212010 |
| language | es |
| publishDate | 2013 |
| publisher | Universidad Nacional Autónoma de México |
| spellingShingle | Implementation of a 10.24 GS/s 12-bit Optoelectronics Analog-to- Digital Converter Based on a Polyphase Demultiplexing Architecture C. Villa-Angulo Ingeniería to poly self synchronized sampling Optoelectronics analog Implementation of a 10.24 GS/s 12-bit Optoelectronics Analog-to- Digital Converter Based on a Polyphase Demultiplexing Architecture C. Villa-Angulo I. O. Hernandez-Fuentes R. Villa-Angulo S. E. Ahumada-Valdez R. A. Ramos-Irigoyen E. Donkor Ingeniería to poly self synchronized sampling Optoelectronics analog In this paper we present the practical implementation of a high-speed polyphase sampling and demultiplexing architecture for optoelectronics analog-to-digital converters (OADCs). The architecture consists of a one-stage divideby- eight decimator circuit where optically-triggered samplers are cascaded to sample an analog input signal, and demultiplex different phases of the sampled signal to yield low data rate for electronic quantization. Electrical-in to electrical-out data format is maintained through the sampling, demultiplexing and quantization processes of the architecture thereby avoiding the need for electrical-to-optical and optical-to-electrical signal conversions. We experimentally demonstrate a 10.24 giga samples per second (GS/s), 12-bit resolution OADC system comprising the optically-triggered sampling circuits integrated with commercial electronic quantizers. Measurements performed on the OADC yielded an effective bit resolution (ENOB) of 10.3 bits, spurious free dynamic range (SFDR) of -32 dB and signal-to-noise and distortion ratio (SNDR) of 63.7 dB. 2013 artículo científico 1665-6423 https://www.redalyc.org/articulo.oa?id=47426212010 es http://www.redalyc.org/revista.oa?id=474 Journal of Applied Research and Technology application/pdf Universidad Nacional Autónoma de México Journal of Applied Research and Technology (México) Num.1 Vol.11 |
| title | Implementation of a 10.24 GS/s 12-bit Optoelectronics Analog-to- Digital Converter Based on a Polyphase Demultiplexing Architecture |
| topic | Ingeniería to poly self synchronized sampling Optoelectronics analog |
| url | https://www.redalyc.org/articulo.oa?id=47426212010 |