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| Format: | Artículo científico |
| Language: | en |
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Universidad Nacional Autónoma de México
2015
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| Online Access: | https://www.redalyc.org/articulo.oa?id=47442802001 |
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| _version_ | 1866585469517561856 |
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| author | Adrian Pedroza de la Crúz |
| author_facet | Adrian Pedroza de la Crúz |
| contents | Characterization and synthesis of a 32-bit asynchronous microprocessor in synchronous reconfigurable devices Adrian Pedroza de la Crúz José Roberto Reyes Barón Susana Ortega Cisneros Juan José Raygoza Panduro Miguel Ángel Carrazco Díaz José Raúl Loo Yau Ingeniería Real time Asynchronous Microprocessor Floating point FPGA delay macro This paper presents the design, implementation, and experimental results of 32-bit asynchronous microprocessor developed in a synchronous reconfigurable device (FPGA), taking advantage of a hard macro. It has support for floating point operations, such as addition, subtraction, and multiplication, and is based on the IEEE 754-2008 standard with 32-bit simple precision. This work describes the different blocks of the microprocessors as delay modules, needed to implement a Self-Timed (ST) protocol in a synchronous system, and the operational analysis of the asynchronous central unit, according to the developed occupations and speeds. The ST control is based on a micropipeline used as a centralized generator of activation signals that permit the performance of the operations in the microprocessor without the need of a global clock. This work compares the asynchronous microprocessor with a synchronous version. The parameters evaluated are power consumption, area, and speed. Both circuits were designed and implemented in an FPGA Virtex 5. The performance obtained was 4 MIPS for the asynchronous microprocessor against 1.6 MIPS for the synchronous. 2015 artículo científico 1665-6423 https://www.redalyc.org/articulo.oa?id=47442802001 en http://www.redalyc.org/revista.oa?id=474 Journal of Applied Research and Technology application/pdf Universidad Nacional Autónoma de México Journal of Applied Research and Technology (México) Num.5 Vol.13 |
| format | Artículo científico |
| id | redalyc_47442802001 |
| language | en |
| publishDate | 2015 |
| publisher | Universidad Nacional Autónoma de México |
| spellingShingle | Characterization and synthesis of a 32-bit asynchronous microprocessor in synchronous reconfigurable devices Adrian Pedroza de la Crúz Ingeniería Real time Asynchronous Microprocessor Floating point FPGA delay macro Characterization and synthesis of a 32-bit asynchronous microprocessor in synchronous reconfigurable devices Adrian Pedroza de la Crúz José Roberto Reyes Barón Susana Ortega Cisneros Juan José Raygoza Panduro Miguel Ángel Carrazco Díaz José Raúl Loo Yau Ingeniería Real time Asynchronous Microprocessor Floating point FPGA delay macro This paper presents the design, implementation, and experimental results of 32-bit asynchronous microprocessor developed in a synchronous reconfigurable device (FPGA), taking advantage of a hard macro. It has support for floating point operations, such as addition, subtraction, and multiplication, and is based on the IEEE 754-2008 standard with 32-bit simple precision. This work describes the different blocks of the microprocessors as delay modules, needed to implement a Self-Timed (ST) protocol in a synchronous system, and the operational analysis of the asynchronous central unit, according to the developed occupations and speeds. The ST control is based on a micropipeline used as a centralized generator of activation signals that permit the performance of the operations in the microprocessor without the need of a global clock. This work compares the asynchronous microprocessor with a synchronous version. The parameters evaluated are power consumption, area, and speed. Both circuits were designed and implemented in an FPGA Virtex 5. The performance obtained was 4 MIPS for the asynchronous microprocessor against 1.6 MIPS for the synchronous. 2015 artículo científico 1665-6423 https://www.redalyc.org/articulo.oa?id=47442802001 en http://www.redalyc.org/revista.oa?id=474 Journal of Applied Research and Technology application/pdf Universidad Nacional Autónoma de México Journal of Applied Research and Technology (México) Num.5 Vol.13 |
| title | Characterization and synthesis of a 32-bit asynchronous microprocessor in synchronous reconfigurable devices |
| topic | Ingeniería Real time Asynchronous Microprocessor Floating point FPGA delay macro |
| url | https://www.redalyc.org/articulo.oa?id=47442802001 |