Static and dynamic task mapping onto network on chip multiprocessors
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| Format: | Artículo científico |
| Language: | en |
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Universidad Nacional de Colombia
2014
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| _version_ | 1876424319556386816 |
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| author | Freddy Bolaños-Martínez |
| author_facet | Freddy Bolaños-Martínez |
| contents | Static and dynamic task mapping onto network on chip multiprocessors Freddy Bolaños-Martínez José Edison Aedo Fredy Rivera-Vélez Ingeniería on Population Task mapping Chip (MPSoC) Multiprocessor System Due to its scalability and flexibility, Network-on-Chip (NoC) is a growing and promising communication paradigm for Multiprocessor System-on-Chip (MPSoC) design. As the manufacturing process scales down to the deep submicron domain and the complexity of the system increases, fault-tolerant design strategies are gaining increased relevance. This paper exhibits the use of a Population-Based Incremental Learning (PBIL) algorithm aimed at finding the best mapping solutions at design time, as well as to finding the optimal remapping solution, in presence of single-node failures on the NoC. The optimization objectives in both cases are the application completion time and the network's peak bandwidth. A deterministic XY routing algorithm was used in order to simulate the traffic conditions in the network which has a 2D mesh topology. Obtained results are promising. The proposed algorithm exhibits a better performance, when compared with other reported approaches, as the problem size increases. 2014 artículo científico 0012-7353 https://www.redalyc.org/articulo.oa?id=49631031005 en http://www.redalyc.org/revista.oa?id=496 Dyna application/pdf Universidad Nacional de Colombia Dyna (Colombia) Num.185 Vol.81 |
| format | Artículo científico |
| id | redalyc_49631031005 |
| institution | Redalyc |
| language | en |
| publishDate | 2014 |
| publisher | Universidad Nacional de Colombia |
| spellingShingle | Static and dynamic task mapping onto network on chip multiprocessors Freddy Bolaños-Martínez Ingeniería on Population Task mapping Chip (MPSoC) Multiprocessor System Static and dynamic task mapping onto network on chip multiprocessors Freddy Bolaños-Martínez José Edison Aedo Fredy Rivera-Vélez Ingeniería on Population Task mapping Chip (MPSoC) Multiprocessor System Due to its scalability and flexibility, Network-on-Chip (NoC) is a growing and promising communication paradigm for Multiprocessor System-on-Chip (MPSoC) design. As the manufacturing process scales down to the deep submicron domain and the complexity of the system increases, fault-tolerant design strategies are gaining increased relevance. This paper exhibits the use of a Population-Based Incremental Learning (PBIL) algorithm aimed at finding the best mapping solutions at design time, as well as to finding the optimal remapping solution, in presence of single-node failures on the NoC. The optimization objectives in both cases are the application completion time and the network's peak bandwidth. A deterministic XY routing algorithm was used in order to simulate the traffic conditions in the network which has a 2D mesh topology. Obtained results are promising. The proposed algorithm exhibits a better performance, when compared with other reported approaches, as the problem size increases. 2014 artículo científico 0012-7353 https://www.redalyc.org/articulo.oa?id=49631031005 en http://www.redalyc.org/revista.oa?id=496 Dyna application/pdf Universidad Nacional de Colombia Dyna (Colombia) Num.185 Vol.81 |
| title | Static and dynamic task mapping onto network on chip multiprocessors |
| topic | Ingeniería on Population Task mapping Chip (MPSoC) Multiprocessor System |
| url | https://www.redalyc.org/articulo.oa?id=49631031005 |