Parallel Hardware/Software Architecture for the BWT and LZ77 Lossless Data Compression Algorithms
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| Format: | Artículo científico |
| Language: | en |
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Instituto Politécnico Nacional
2006
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| _version_ | 1876429833453436928 |
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| author | Virgilio Zuñiga Grajeda |
| author_facet | Virgilio Zuñiga Grajeda |
| contents | Parallel Hardware/Software Architecture for the BWT and LZ77 Lossless Data Compression Algorithms Virgilio Zuñiga Grajeda Claudia Feregrino Uribe Rene Cumplido Parra Computación Ziv LEON2 Lempel Burrows Coprocessor Nowadays, the use of digital communication systems has increased in such a way that network bandwidth is affected. This problem can be solved by implementing data compression algorithms in communication devices to reduce the amount of data to be transmitted. However, the design of large hardware data compression models implies to consider an efficient use of the silicon area. This work proposes the conjunction of two different hardware lossless data compression approaches which share common hardware elements. The project also involves the design of a hardware/software architecture to exploit parallelism increasing execution speed while keeping flexibility. A custom coprocessor unit executes the compute-intense tasks of the Burrows-Wheeler Transform and the Lempel-Ziv lossless data compression schemes. This coprocessor unit is controlled by a SPARC V8 compatible general purpose microprocessor called LEON2 2006 artículo científico 1405-5546 https://www.redalyc.org/articulo.oa?id=61500206 en http://www.redalyc.org/revista.oa?id=615 Computación y Sistemas application/pdf Instituto Politécnico Nacional Computación y Sistemas (México) Num.2 Vol.10 |
| format | Artículo científico |
| id | redalyc_61500206 |
| institution | Redalyc |
| language | en |
| publishDate | 2006 |
| publisher | Instituto Politécnico Nacional |
| spellingShingle | Parallel Hardware/Software Architecture for the BWT and LZ77 Lossless Data Compression Algorithms Virgilio Zuñiga Grajeda Computación Ziv LEON2 Lempel Burrows Coprocessor Parallel Hardware/Software Architecture for the BWT and LZ77 Lossless Data Compression Algorithms Virgilio Zuñiga Grajeda Claudia Feregrino Uribe Rene Cumplido Parra Computación Ziv LEON2 Lempel Burrows Coprocessor Nowadays, the use of digital communication systems has increased in such a way that network bandwidth is affected. This problem can be solved by implementing data compression algorithms in communication devices to reduce the amount of data to be transmitted. However, the design of large hardware data compression models implies to consider an efficient use of the silicon area. This work proposes the conjunction of two different hardware lossless data compression approaches which share common hardware elements. The project also involves the design of a hardware/software architecture to exploit parallelism increasing execution speed while keeping flexibility. A custom coprocessor unit executes the compute-intense tasks of the Burrows-Wheeler Transform and the Lempel-Ziv lossless data compression schemes. This coprocessor unit is controlled by a SPARC V8 compatible general purpose microprocessor called LEON2 2006 artículo científico 1405-5546 https://www.redalyc.org/articulo.oa?id=61500206 en http://www.redalyc.org/revista.oa?id=615 Computación y Sistemas application/pdf Instituto Politécnico Nacional Computación y Sistemas (México) Num.2 Vol.10 |
| title | Parallel Hardware/Software Architecture for the BWT and LZ77 Lossless Data Compression Algorithms |
| topic | Computación Ziv LEON2 Lempel Burrows Coprocessor |
| url | https://www.redalyc.org/articulo.oa?id=61500206 |