New High-Performance Full Adders Using an Alternative Logic Structure
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| Format: | Artículo científico |
| Langue: | en |
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Instituto Politécnico Nacional
2011
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| _version_ | 1876475270143148032 |
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| author | Mónico Linares Aranda |
| author_facet | Mónico Linares Aranda |
| contents | New High-Performance Full Adders Using an Alternative Logic Structure Mónico Linares Aranda Mariano Aguirre Hernández Computación Low Full adder power Pipeline This paper presents two new high-speed low-power 1-bit full-adder cells using an alternative logic structure, and the logic styles DPL and SR-CPL. The adders were designed using electrical parameters of a 0.35µm Complementary Metal-Oxide-Semiconductor (CMOS) process, and were compared with various adders published previously, with regards of power-delay product. To validate the performance simulation results of one of the proposed adders, an 8-bits pipelined multiplier was fabricated using a 0.35µm CMOS technology, and it showed to provide superior performance. 2011 artículo científico 1405-5546 https://www.redalyc.org/articulo.oa?id=61520765002 en http://www.redalyc.org/revista.oa?id=615 Computación y Sistemas application/pdf Instituto Politécnico Nacional Computación y Sistemas (México) Num.3 Vol.14 |
| format | Artículo científico |
| id | redalyc_61520765002 |
| institution | Redalyc |
| language | en |
| publishDate | 2011 |
| publisher | Instituto Politécnico Nacional |
| spellingShingle | New High-Performance Full Adders Using an Alternative Logic Structure Mónico Linares Aranda Computación Low Full adder power Pipeline New High-Performance Full Adders Using an Alternative Logic Structure Mónico Linares Aranda Mariano Aguirre Hernández Computación Low Full adder power Pipeline This paper presents two new high-speed low-power 1-bit full-adder cells using an alternative logic structure, and the logic styles DPL and SR-CPL. The adders were designed using electrical parameters of a 0.35µm Complementary Metal-Oxide-Semiconductor (CMOS) process, and were compared with various adders published previously, with regards of power-delay product. To validate the performance simulation results of one of the proposed adders, an 8-bits pipelined multiplier was fabricated using a 0.35µm CMOS technology, and it showed to provide superior performance. 2011 artículo científico 1405-5546 https://www.redalyc.org/articulo.oa?id=61520765002 en http://www.redalyc.org/revista.oa?id=615 Computación y Sistemas application/pdf Instituto Politécnico Nacional Computación y Sistemas (México) Num.3 Vol.14 |
| title | New High-Performance Full Adders Using an Alternative Logic Structure |
| topic | Computación Low Full adder power Pipeline |
| url | https://www.redalyc.org/articulo.oa?id=61520765002 |