A Reorder Buffer Design for High Performance Processors

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Autore principale: José R. García Ordaz
Natura: Artículo científico
Lingua:en
Pubblicazione: Instituto Politécnico Nacional 2012
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author José R. García Ordaz
author_facet José R. García Ordaz
contents A Reorder Buffer Design for High Performance Processors José R. García Ordaz Marco A. Ramírez Salinas Luis A. Villa Vargas Herón Molina Lozano Cuauhtémoc Peredo Macías Computación buffer reorder instruction window low power consumption Superscalar processors Modern reorder buffers (ROBs) were conceived to improve processor performance by allowing instruction execution out of the original program order and run ahead of sequential instruction code exploiting existing instruction level parallelism (ILP). The ROB is a functional structure of a processor execution engine that supports speculative execution, physical register recycling, and precise exception recovering. Traditionally, the ROB is considered as a monolithic circular buffer with incoming instructions at the tail pointer after the decoding stage and completing instructions at the head pointer after the commitment stage. The latter stage verifies instructions that have been dispatched, issued, executed, and are not completed speculatively. This paper presents a design of distributed reorder buffer microarchitecture by using small structures near building blocks which work together, using the same tail and head pointer values on all structures for synchronization. The reduction of area, and therefore, the reduction of power and delay make this design suitable for both embedded and high performance microprocessors. 2012 artículo científico 1405-5546 https://www.redalyc.org/articulo.oa?id=61523304003 en http://www.redalyc.org/revista.oa?id=615 Computación y Sistemas application/pdf Instituto Politécnico Nacional Computación y Sistemas (México) Num.1 Vol.16
format Artículo científico
id redalyc_61523304003
institution Redalyc
language en
publishDate 2012
publisher Instituto Politécnico Nacional
spellingShingle A Reorder Buffer Design for High Performance Processors
José R. García Ordaz
Computación
buffer
reorder
instruction window
low power consumption
Superscalar processors
A Reorder Buffer Design for High Performance Processors José R. García Ordaz Marco A. Ramírez Salinas Luis A. Villa Vargas Herón Molina Lozano Cuauhtémoc Peredo Macías Computación buffer reorder instruction window low power consumption Superscalar processors Modern reorder buffers (ROBs) were conceived to improve processor performance by allowing instruction execution out of the original program order and run ahead of sequential instruction code exploiting existing instruction level parallelism (ILP). The ROB is a functional structure of a processor execution engine that supports speculative execution, physical register recycling, and precise exception recovering. Traditionally, the ROB is considered as a monolithic circular buffer with incoming instructions at the tail pointer after the decoding stage and completing instructions at the head pointer after the commitment stage. The latter stage verifies instructions that have been dispatched, issued, executed, and are not completed speculatively. This paper presents a design of distributed reorder buffer microarchitecture by using small structures near building blocks which work together, using the same tail and head pointer values on all structures for synchronization. The reduction of area, and therefore, the reduction of power and delay make this design suitable for both embedded and high performance microprocessors. 2012 artículo científico 1405-5546 https://www.redalyc.org/articulo.oa?id=61523304003 en http://www.redalyc.org/revista.oa?id=615 Computación y Sistemas application/pdf Instituto Politécnico Nacional Computación y Sistemas (México) Num.1 Vol.16
title A Reorder Buffer Design for High Performance Processors
topic Computación
buffer
reorder
instruction window
low power consumption
Superscalar processors
url https://www.redalyc.org/articulo.oa?id=61523304003