Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures
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| Format: | Artículo científico |
| Langue: | en |
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Universidad Nacional de La Plata
2006
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| _version_ | 1876428499879723008 |
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| author | Francisco J. Villa |
| author_facet | Francisco J. Villa |
| contents | Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures Francisco J. Villa Manuel Acacio Sánchez José Manuel García Carrasco Computación Chip Energy multiprocessors Aware Techniques Cache Storage Use Chip-multiprocessor systems or CMPs have emerged as a high-perfomance organization for the increasing number of transistors available on a chip, and are projected to dominate the market of server and desktop computers. CMPs require innovative designs of on-chip memory hierarchies, especially designed to address the problems that arise in this novel kind of architecture: higher memory bandwidh demand from more processing cores and the increasing latency of off-chip cache misses. Moreover, the energy consumption topic is even more pressing than in traditionalmultiprocessors, as the CMPs are commonly used in embedded systems. This paper presents a survey of some of the proposals that have recently appeared facing these topics. 2006 artículo científico 1666-6046 https://www.redalyc.org/articulo.oa?id=638067342003 en http://www.redalyc.org/revista.oa?id=6380 Journal of Computer Science and Technology application/pdf Universidad Nacional de La Plata Journal of Computer Science and Technology (Argentina) Num.01 Vol.6 |
| format | Artículo científico |
| id | redalyc_638067342003 |
| institution | Redalyc |
| language | en |
| publishDate | 2006 |
| publisher | Universidad Nacional de La Plata |
| spellingShingle | Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures Francisco J. Villa Computación Chip Energy multiprocessors Aware Techniques Cache Storage Use Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures Francisco J. Villa Manuel Acacio Sánchez José Manuel García Carrasco Computación Chip Energy multiprocessors Aware Techniques Cache Storage Use Chip-multiprocessor systems or CMPs have emerged as a high-perfomance organization for the increasing number of transistors available on a chip, and are projected to dominate the market of server and desktop computers. CMPs require innovative designs of on-chip memory hierarchies, especially designed to address the problems that arise in this novel kind of architecture: higher memory bandwidh demand from more processing cores and the increasing latency of off-chip cache misses. Moreover, the energy consumption topic is even more pressing than in traditionalmultiprocessors, as the CMPs are commonly used in embedded systems. This paper presents a survey of some of the proposals that have recently appeared facing these topics. 2006 artículo científico 1666-6046 https://www.redalyc.org/articulo.oa?id=638067342003 en http://www.redalyc.org/revista.oa?id=6380 Journal of Computer Science and Technology application/pdf Universidad Nacional de La Plata Journal of Computer Science and Technology (Argentina) Num.01 Vol.6 |
| title | Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures |
| topic | Computación Chip Energy multiprocessors Aware Techniques Cache Storage Use |
| url | https://www.redalyc.org/articulo.oa?id=638067342003 |