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  • Verification of a Fabless Device Model Using TCAD Tools: from Bipolar Transistor Formation to I-V Characteristics Extraction
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Verification of a Fabless Device Model Using TCAD Tools: from Bipolar Transistor Formation to I-V Characteristics Extraction

Fuente: Redalyc
Salvato in:
Dettagli Bibliografici
Autore principale: Vaidotas Barzdenas
Natura: Artículo científico
Lingua:en
Pubblicazione: Universidad Nacional de Colombia 2021
Soggetti:
Ingeniería
TCAD tools
learning technology
laboratory learning environment
Electronics engineering education
Accesso online:
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Accesso online

https://www.redalyc.org/articulo.oa?id=64379876009
https://www.redalyc.org/journal/643/64379876009/
https://www.redalyc.org/journal/643/64379876009/html/
https://www.redalyc.org/journal/643/64379876009/64379876009.epub
https://www.redalyc.org/journal/643/64379876009/movil

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