Processing techniques for 3-D integration techniques
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| Format: | Artículo científico |
| Language: | en |
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Sociedad Mexicana de Ciencia y Tecnología de Superficies y Materiales A.C.
2001
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| _version_ | 1876461578990125056 |
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| author | S. Burkett |
| author_facet | S. Burkett |
| contents | Processing techniques for 3-D integration techniques S. Burkett C. Craigie X. Qiao D. Temple B. Stoner G. McGuire Física, Astronomía y Matemáticas wafer Through Adhesion Interconnect Electroplating Processing techniques that address the interconnect issues required for fabrication of deep sub-micron electronic devicesand for three-dimensional (3-D) integration of these components will be described. As the interconnect density increases,alternate methods of providing input/output (I/O) leads on a chip are required. One attractive approach to providingincreased connectivity is to use through-wafer interconnects. This reduces the interconnect density on the front surfacewhile providing additional I/Os on the back surface. It also provides a convenient mechanism for integrating two or moredie to form a 3-D integrated structure. Processing techniques under development include: high aspect ratio silicon etching,insulator lining, adhesion/barrier layer deposition, seed layer deposition, electroplating, and chemical mechanicalplanarization (CMP).The primary challenge to implementing 3-D stacking is the formation of high aspect ratio interconnects with a sufficientlysmall diameter and, consequently, with sufficiently high density. The techniques used for fabrication of the verticalinterconnects need to be compatible with CMOS technology and executed within the thermal budget of completed ICs. 2001 artículo científico 1665-3521 https://www.redalyc.org/articulo.oa?id=94201301 en http://www.redalyc.org/revista.oa?id=942 Superficies y vacío application/pdf Sociedad Mexicana de Ciencia y Tecnología de Superficies y Materiales A.C. Superficies y vacío (México) Num.13 |
| format | Artículo científico |
| id | redalyc_94201301 |
| institution | Redalyc |
| language | en |
| publishDate | 2001 |
| publisher | Sociedad Mexicana de Ciencia y Tecnología de Superficies y Materiales A.C. |
| spellingShingle | Processing techniques for 3-D integration techniques S. Burkett Física, Astronomía y Matemáticas wafer Through Adhesion Interconnect Electroplating Processing techniques for 3-D integration techniques S. Burkett C. Craigie X. Qiao D. Temple B. Stoner G. McGuire Física, Astronomía y Matemáticas wafer Through Adhesion Interconnect Electroplating Processing techniques that address the interconnect issues required for fabrication of deep sub-micron electronic devicesand for three-dimensional (3-D) integration of these components will be described. As the interconnect density increases,alternate methods of providing input/output (I/O) leads on a chip are required. One attractive approach to providingincreased connectivity is to use through-wafer interconnects. This reduces the interconnect density on the front surfacewhile providing additional I/Os on the back surface. It also provides a convenient mechanism for integrating two or moredie to form a 3-D integrated structure. Processing techniques under development include: high aspect ratio silicon etching,insulator lining, adhesion/barrier layer deposition, seed layer deposition, electroplating, and chemical mechanicalplanarization (CMP).The primary challenge to implementing 3-D stacking is the formation of high aspect ratio interconnects with a sufficientlysmall diameter and, consequently, with sufficiently high density. The techniques used for fabrication of the verticalinterconnects need to be compatible with CMOS technology and executed within the thermal budget of completed ICs. 2001 artículo científico 1665-3521 https://www.redalyc.org/articulo.oa?id=94201301 en http://www.redalyc.org/revista.oa?id=942 Superficies y vacío application/pdf Sociedad Mexicana de Ciencia y Tecnología de Superficies y Materiales A.C. Superficies y vacío (México) Num.13 |
| title | Processing techniques for 3-D integration techniques |
| topic | Física, Astronomía y Matemáticas wafer Through Adhesion Interconnect Electroplating |
| url | https://www.redalyc.org/articulo.oa?id=94201301 |